timing(Vector,Decode): judge isComplex by inst encoding directly (#4066)
fix(aes): fix exception check for aes64ks1i.rnum of aes64ks1i must be in the range 0x0..0xA. The values 0xB..0xF are reserved.
fix(vector, decode): use OPFV[VF] encoded in inst to check if need FS not Off (#3696)* When FS is Off, executing vfslide1up/down should raise illegal instruction exception
rv64v: fix fp type generate in exceptionGen and add check for vwsll (#3233)
Decode: let CSRR vl executed in Vsetu
Backend: add CSRR PseudoInstruction
vtype: add illegal check when modified reserved bits of vtype (#3170)
rv64v: implement lsu & lsq vector datapath
RiscvInst: add vector load/store function
RiscvInst: change OPCODE field to instr[6:0]
merge master into new-backendTodo: fix error
Predecode: fix ebreak predecoded as jalr (#2186)
mod: refactor the code of encoding
isa-riscv: add Vector CATEGORY fields
isa-riscv: refactor BitFields
isa-riscv,vector: add bundles and convert function* Add class VType, VConfig* Add object VSew, VLmul
isa-riscv: add bitfields of riscv 32-bit inst
Merge branch 'decoupled-frontend-ifu' into decoupled-frontend
PreDecode: add exception logic* set instruction to NOP when exception
misc: update PCL information (#899)XiangShan is jointly released by ICT and PCL.
Add MulanPSL-2.0 License (#824)In this commit, we add License for XiangShan project.
clean up deprecated decode codes
[WIP] Merge debian-gogogo into xs-fpu
rvc: disable C_F floating-point instructions
FPU: support rvc
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