1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package top 18 19import chisel3._ 20import chipsalliance.rocketchip.config 21import device._ 22import freechips.rocketchip.amba.axi4.{AXI4EdgeParameters, AXI4MasterNode, AXI4Xbar} 23import freechips.rocketchip.diplomacy.{AddressSet, InModuleBody, LazyModule, LazyModuleImp} 24 25class SimMMIO(edge: AXI4EdgeParameters)(implicit p: config.Parameters) extends LazyModule { 26 27 val node = AXI4MasterNode(List(edge.master)) 28 29 val flash = LazyModule(new AXI4Flash(Seq(AddressSet(0x10000000L, 0xfffffff)))) 30 val uart = LazyModule(new AXI4UART(Seq(AddressSet(0x40600000L, 0xf)))) 31 val vga = LazyModule(new AXI4VGA( 32 sim = false, 33 fbAddress = Seq(AddressSet(0x50000000L, 0x3fffffL)), 34 ctrlAddress = Seq(AddressSet(0x40001000L, 0x7L)) 35 )) 36 val sd = LazyModule(new AXI4DummySD(Seq(AddressSet(0x40002000L, 0xfff)))) 37 val intrGen = LazyModule(new AXI4IntrGenerator(Seq(AddressSet(0x40070000L, 0x0000ffffL)))) 38 39 val axiBus = AXI4Xbar() 40 41 uart.node := axiBus 42 vga.node :*= axiBus 43 flash.node := axiBus 44 sd.node := axiBus 45 intrGen.node := axiBus 46 47 axiBus := node 48 49 val io_axi4 = InModuleBody { 50 node.makeIOs() 51 } 52 53 def connectToSoC(soc: HaveAXI4PeripheralPort) = { 54 io_axi4 <> soc.peripheral 55 } 56 57 lazy val module = new LazyModuleImp(this){ 58 val io = IO(new Bundle() { 59 val uart = new UARTIO 60 val interrupt = new IntrGenIO 61 }) 62 io.uart <> uart.module.io.extra.get 63 io.interrupt <> intrGen.module.io.extra.get 64 } 65 66} 67