1package xiangshan.backend.decode.isa.bitfield 2 3import chisel3._ 4 5abstract class RiscvInst(bitWidth: Int) extends Bundle { 6 val inst: UInt = UInt(bitWidth.W) 7} 8 9class Riscv32BitInst extends RiscvInst(32) { 10 def ALL : UInt = inst 11 def OPCODE : UInt = inst( 6, 0) 12 def RD : UInt = inst(11, 7) 13 def FUNCT3 : UInt = inst(14, 12) 14 def RS1 : UInt = inst(19, 15) 15 def RS2 : UInt = inst(24, 20) 16 def FUNCT7 : UInt = inst(31, 25) 17 def OPCODE5Bit: UInt = inst( 6, 2) 18} 19 20trait BitFieldsI { this: Riscv32BitInst => 21 def IMM12 : UInt = inst(31, 20) 22 def SHAMT6 : UInt = inst(25, 20) 23 def SHAMT5 : UInt = inst(24, 20) 24} 25 26trait BitFieldsS { this: Riscv32BitInst => 27 def IMM5 : UInt = inst(11, 7) 28 def IMM7 : UInt = inst(31, 25) 29} 30 31trait BitFieldsCSR { this: Riscv32BitInst => 32 def CSRIDX : UInt = inst(31, 20) 33 def CSRIMM : UInt = inst(19, 15) 34} 35 36trait BitFieldsFp { this: Riscv32BitInst => 37 def FD : UInt = inst(11, 7) 38 def FS1 : UInt = inst(19, 15) 39 def FS2 : UInt = inst(24, 20) 40 def FS3 : UInt = inst(31, 27) 41 def RM : UInt = inst(14, 12) // round mode 42 def CONV_SGN: UInt = inst(24, 20) 43 def FMT : UInt = inst(26, 25) 44 def TYP : UInt = inst(21, 20) 45} 46 47trait BitFieldsVec { this: Riscv32BitInst => 48 def VCATEGORY : UInt = inst(14, 12) 49 def NF : UInt = inst(31, 29) 50 def MEW : UInt = inst(28) 51 def MOP : UInt = inst(27, 26) 52 def VM : UInt = inst(25) 53 def LUMOP : UInt = inst(24, 20) 54 def SUMOP : UInt = inst(24, 20) 55 def WIDTH : UInt = inst(14, 12) 56 def VD : UInt = inst(11, 7) 57 def VS1 : UInt = inst(19, 15) 58 def VS2 : UInt = inst(24, 20) 59 def VS3 : UInt = inst(11, 7) 60 def FUNCT6 : UInt = inst(31 ,26) 61 def ZIMM_VSETVLI : UInt = inst(30, 20) 62 def ZIMM_VSETIVLI : UInt = inst(29, 20) 63 def UIMM_VSETIVLI : UInt = inst(19, 15) 64 def IMM5_OPIVI : UInt = inst(19, 15) 65 66 def getInstVType : InstVType = { 67 val res = Wire(new InstVType) 68 res.vlmul := ZIMM_VSETVLI(2, 0) 69 res.vsew := ZIMM_VSETVLI(5, 3) 70 res.vta := ZIMM_VSETVLI(6) 71 res.vma := ZIMM_VSETVLI(7) 72 res 73 } 74 75 def isVecStore = { 76 this.OPCODE === "b0100111".U && (this.WIDTH === 0.U || this.WIDTH(2) === 1.B) 77 } 78 79 def isVecLoad = { 80 this.OPCODE === "b0000111".U && (this.WIDTH === 0.U || this.WIDTH(2) === 1.B) 81 } 82} 83 84class XSInstBitFields extends Riscv32BitInst 85 with BitFieldsI 86 with BitFieldsS 87 with BitFieldsCSR 88 with BitFieldsFp 89 with BitFieldsVec 90 91class InstVType extends Bundle { 92 val reserved = UInt(3.W) 93 val vma = Bool() 94 val vta = Bool() 95 val vsew = UInt(3.W) 96 val vlmul = UInt(3.W) 97} 98 99object OPCODE5Bit { 100 val LOAD = "b00_000".U 101 val LOAD_FP = "b00_001".U 102 val CUSTOM_0 = "b00_010".U 103 val MSIC_MEM = "b00_011".U 104 val OP_IMM = "b00_100".U 105 val AUIPC = "b00_101".U 106 val OP_IMM_32 = "b00_110".U 107 val INST48b_0 = "b00_111".U 108 109 val STORE = "b01_000".U 110 val STORE_FP = "b01_001".U 111 val CUSTOM_1 = "b01_010".U 112 val AMO = "b01_011".U 113 val OP = "b01_100".U 114 val LUI = "b01_101".U 115 val OP_32 = "b01_110".U 116 val INST64b = "b01_111".U 117 118 val MADD = "b10_000".U 119 val MSUB = "b10_001".U 120 val NMSUB = "b10_010".U 121 val NMADD = "b10_011".U 122 val OP_FP = "b10_100".U 123 val OP_V = "b10_101".U 124 val CUSTOM_2 = "b10_110".U 125 val INST48b_1 = "b10_111".U 126 127 val BRANCH = "b11_000".U 128 val JALR = "b11_001".U 129 val RESERVED_0 = "b11_010".U 130 val JAL = "b11_011".U 131 val SYSTEM = "b11_100".U 132 val RESERVED_1 = "b11_101".U 133 val CUSTOM_3 = "b11_110".U 134 val INSTge80b = "b11_111".U 135} 136