1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* 4* XiangShan is licensed under Mulan PSL v2. 5* You can use this software according to the terms and conditions of the Mulan PSL v2. 6* You may obtain a copy of Mulan PSL v2 at: 7* http://license.coscl.org.cn/MulanPSL2 8* 9* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 10* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 11* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 12* 13* See the Mulan PSL v2 for more details. 14***************************************************************************************/ 15 16package device 17 18import chisel3._ 19import chisel3.util._ 20import chipsalliance.rocketchip.config.Parameters 21import freechips.rocketchip.diplomacy.AddressSet 22import utils._ 23 24class UARTIO extends Bundle { 25 val out = new Bundle { 26 val valid = Output(Bool()) 27 val ch = Output(UInt(8.W)) 28 } 29 val in = new Bundle { 30 val valid = Output(Bool()) 31 val ch = Input(UInt(8.W)) 32 } 33} 34 35class AXI4UART 36( 37 address: Seq[AddressSet] 38)(implicit p: Parameters) 39 extends AXI4SlaveModule(address, executable = false, _extra = new UARTIO) 40{ 41 override lazy val module = new AXI4SlaveModuleImp[UARTIO](this){ 42 val rxfifo = RegInit(0.U(32.W)) 43 val txfifo = Reg(UInt(32.W)) 44 val stat = RegInit(1.U(32.W)) 45 val ctrl = RegInit(0.U(32.W)) 46 47 io.extra.get.out.valid := (waddr(3,0) === 4.U && in.w.fire()) 48 io.extra.get.out.ch := in.w.bits.data(7,0) 49 io.extra.get.in.valid := (raddr(3,0) === 0.U && in.r.fire()) 50 51 val mapping = Map( 52 RegMap(0x0, io.extra.get.in.ch, RegMap.Unwritable), 53 RegMap(0x4, txfifo), 54 RegMap(0x8, stat), 55 RegMap(0xc, ctrl) 56 ) 57 58 RegMap.generate(mapping, raddr(3,0), in.r.bits.data, 59 waddr(3,0), in.w.fire(), in.w.bits.data, MaskExpand(in.w.bits.strb >> waddr(2,0)) 60 ) 61 } 62} 63