1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* 4* XiangShan is licensed under Mulan PSL v2. 5* You can use this software according to the terms and conditions of the Mulan PSL v2. 6* You may obtain a copy of Mulan PSL v2 at: 7* http://license.coscl.org.cn/MulanPSL2 8* 9* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 10* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 11* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 12* 13* See the Mulan PSL v2 for more details. 14***************************************************************************************/ 15 16package device 17 18import chisel3._ 19import chisel3.util._ 20import chipsalliance.rocketchip.config.Parameters 21import freechips.rocketchip.diplomacy.AddressSet 22import utils._ 23 24// we support 256 interrupt bits by default 25class IntrGenIO extends Bundle { 26 val intrVec = Output(UInt(256.W)) 27} 28 29class AXI4IntrGenerator 30( 31 address: Seq[AddressSet] 32)(implicit p: Parameters) 33 extends AXI4SlaveModule(address, executable = false, _extra = new IntrGenIO) 34{ 35 36 override lazy val module = new AXI4SlaveModuleImp(this){ 37 38 val intrReg = RegInit(VecInit(Seq.fill(8)(0.U(32.W)))) 39 io.extra.get.intrVec := Cat(intrReg.reverse) 40 41 when (in.w.fire()) { 42 intrReg(waddr(4, 2)) := in.w.bits.data(31, 0) 43 } 44 45 in.r.bits.data := intrReg(raddr) 46 } 47} 48