1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* 4* XiangShan is licensed under Mulan PSL v2. 5* You can use this software according to the terms and conditions of the Mulan PSL v2. 6* You may obtain a copy of Mulan PSL v2 at: 7* http://license.coscl.org.cn/MulanPSL2 8* 9* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 10* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 11* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 12* 13* See the Mulan PSL v2 for more details. 14***************************************************************************************/ 15 16package top 17 18import chisel3._ 19import chisel3.util._ 20import xiangshan._ 21import utils._ 22import system._ 23import chipsalliance.rocketchip.config._ 24import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, XLen} 25import sifive.blocks.inclusivecache.{InclusiveCache, InclusiveCacheMicroParameters, CacheParameters} 26import xiangshan.backend.dispatch.DispatchParameters 27import xiangshan.cache.{DCacheParameters, ICacheParameters, L1plusCacheParameters} 28import xiangshan.cache.prefetch.{BOPParameters, L1plusPrefetcherParameters, L2PrefetcherParameters, StreamPrefetchParameters} 29 30class DefaultConfig(n: Int) extends Config((site, here, up) => { 31 case XLen => 64 32 case DebugOptionsKey => DebugOptions() 33 case SoCParamsKey => SoCParameters( 34 cores = List.tabulate(n){ i => XSCoreParameters(HartId = i) } 35 ) 36}) 37 38// Synthesizable minimal XiangShan 39// * It is still an out-of-order, super-scalaer arch 40// * L1 cache included 41// * L2 cache NOT included 42// * L3 cache included 43class MinimalConfig(n: Int = 1) extends Config( 44 new DefaultConfig(n).alter((site, here, up) => { 45 case SoCParamsKey => up(SoCParamsKey).copy( 46 cores = up(SoCParamsKey).cores.map(_.copy( 47 DecodeWidth = 2, 48 RenameWidth = 2, 49 FetchWidth = 4, 50 IssQueSize = 8, 51 NRPhyRegs = 80, 52 LoadQueueSize = 16, 53 StoreQueueSize = 16, 54 RoqSize = 32, 55 BrqSize = 8, 56 FtqSize = 16, 57 IBufSize = 16, 58 StoreBufferSize = 4, 59 StoreBufferThreshold = 3, 60 dpParams = DispatchParameters( 61 IntDqSize = 8, 62 FpDqSize = 8, 63 LsDqSize = 8, 64 IntDqDeqWidth = 4, 65 FpDqDeqWidth = 4, 66 LsDqDeqWidth = 4 67 ), 68 icacheParameters = ICacheParameters( 69 nSets = 8, // 4KB ICache 70 tagECC = Some("parity"), 71 dataECC = Some("parity"), 72 replacer = Some("setplru"), 73 nMissEntries = 2 74 ), 75 dcacheParameters = DCacheParameters( 76 nSets = 8, // 4KB DCache 77 nWays = 4, 78 tagECC = Some("secded"), 79 dataECC = Some("secded"), 80 replacer = Some("setplru"), 81 nMissEntries = 4, 82 nProbeEntries = 4, 83 nReleaseEntries = 4, 84 nStoreReplayEntries = 4, 85 ), 86 L2Size = 16 * 1024, // 16KB 87 L2NWays = 8, 88 EnableBPD = false, // disable TAGE 89 EnableLoop = false, 90 TlbEntrySize = 4, 91 TlbSPEntrySize = 2, 92 PtwL1EntrySize = 2, 93 PtwL2EntrySize = 64, 94 PtwL3EntrySize = 128, 95 PtwSPEntrySize = 2, 96 useFakeL2Cache = true, 97 )), 98 L3Size = 32 * 1024, // 32KB 99 ) 100 }) 101) 102 103// Non-synthesizable MinimalConfig, for fast simulation only 104class MinimalSimConfig(n: Int = 1) extends Config( 105 new MinimalConfig(n).alter((site, here, up) => { 106 case SoCParamsKey => up(SoCParamsKey).copy( 107 cores = up(SoCParamsKey).cores.map(_.copy( 108 useFakeDCache = true, 109 useFakePTW = true, 110 useFakeL1plusCache = true, 111 )), 112 useFakeL3Cache = true 113 ) 114 }) 115) 116