1package xiangshan.backend.issue 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import xiangshan._ 8import xiangshan.backend.Bundles 9import xiangshan.backend.datapath.DataConfig.VAddrData 10import xiangshan.backend.regfile.RfWritePortWithConfig 11import xiangshan.backend.rename.BusyTable 12import xiangshan.mem.{LsqEnqCtrl, LsqEnqIO, MemWaitUpdateReq, SqPtr} 13import xiangshan.backend.Bundles.{DynInst, IssueQueueWakeUpBundle} 14 15sealed trait SchedulerType 16 17case class IntScheduler() extends SchedulerType 18case class MemScheduler() extends SchedulerType 19case class VfScheduler() extends SchedulerType 20case class NoScheduler() extends SchedulerType 21 22class Scheduler(val params: SchdBlockParams)(implicit p: Parameters) extends LazyModule with HasXSParameter { 23 val numIntStateWrite = backendParams.numIntWb 24 val numVfStateWrite = backendParams.numVfWb 25 26 val dispatch2Iq = LazyModule(new Dispatch2Iq(params)) 27 val issueQueue = params.issueBlockParams.map(x => LazyModule(new IssueQueue(x).suggestName(x.getIQName))) 28 29 lazy val module = params.schdType match { 30 case IntScheduler() => new SchedulerArithImp(this)(params, p) 31 case MemScheduler() => new SchedulerMemImp(this)(params, p) 32 case VfScheduler() => new SchedulerArithImp(this)(params, p) 33 case _ => null 34 } 35} 36 37class SchedulerIO()(implicit params: SchdBlockParams, p: Parameters) extends XSBundle { 38 // params alias 39 private val LoadQueueSize = VirtualLoadQueueSize 40 41 val fromTop = new Bundle { 42 val hartId = Input(UInt(8.W)) 43 } 44 val fromCtrlBlock = new Bundle { 45 val pcVec = Input(Vec(params.numPcReadPort, UInt(VAddrData().dataWidth.W))) 46 val targetVec = Input(Vec(params.numPcReadPort, UInt(VAddrData().dataWidth.W))) 47 val flush = Flipped(ValidIO(new Redirect)) 48 } 49 val fromDispatch = new Bundle { 50 val allocPregs = Vec(RenameWidth, Input(new ResetPregStateReq)) 51 val uops = Vec(params.numUopIn, Flipped(DecoupledIO(new DynInst))) 52 } 53 val intWriteBack = MixedVec(Vec(backendParams.intPregParams.numWrite, 54 new RfWritePortWithConfig(backendParams.intPregParams.dataCfg, backendParams.intPregParams.addrWidth))) 55 val vfWriteBack = MixedVec(Vec(backendParams.vfPregParams.numWrite, 56 new RfWritePortWithConfig(backendParams.vfPregParams.dataCfg, backendParams.vfPregParams.addrWidth))) 57 val toDataPath: MixedVec[MixedVec[DecoupledIO[Bundles.IssueQueueIssueBundle]]] = MixedVec(params.issueBlockParams.map(_.genIssueDecoupledBundle)) 58 val fromDataPath: MixedVec[MixedVec[Bundles.OGRespBundle]] = MixedVec(params.issueBlockParams.map(x => Flipped(x.genOGRespBundle))) 59 60 val memIO = if (params.isMemSchd) Some(new Bundle { 61 val lsqEnqIO = Flipped(new LsqEnqIO) 62 }) else None 63 val fromMem = if (params.isMemSchd) Some(new Bundle { 64 val ldaFeedback = Flipped(Vec(params.LduCnt, new MemRSFeedbackIO)) 65 val staFeedback = Flipped(Vec(params.StaCnt, new MemRSFeedbackIO)) 66 val stIssuePtr = Input(new SqPtr()) 67 val lcommit = Input(UInt(log2Up(CommitWidth + 1).W)) 68 val scommit = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) // connected to `memBlock.io.sqDeq` instead of ROB 69 // from lsq 70 val lqCancelCnt = Input(UInt(log2Up(LoadQueueSize + 1).W)) 71 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 72 val memWaitUpdateReq = Flipped(new MemWaitUpdateReq) 73 }) else None 74 val toMem = if (params.isMemSchd) Some(new Bundle { 75 val loadFastMatch = Output(Vec(params.LduCnt, new IssueQueueLoadBundle)) 76 }) else None 77} 78 79abstract class SchedulerImpBase(wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 80 extends LazyModuleImp(wrapper) 81 with HasXSParameter 82{ 83 val io = IO(new SchedulerIO()) 84 85 // alias 86 private val schdType = params.schdType 87 private val (numRfRead, numRfWrite) = params.numRfReadWrite.getOrElse((0, 0)) 88 private val numPregs = params.numPregs 89 90 // Modules 91 val dispatch2Iq: Dispatch2IqImp = wrapper.dispatch2Iq.module 92 val issueQueues: Seq[IssueQueueImp] = wrapper.issueQueue.map(_.module) 93 94 // BusyTable Modules 95 val intBusyTable = schdType match { 96 case IntScheduler() | MemScheduler() => Some(Module(new BusyTable(dispatch2Iq.numIntStateRead, wrapper.numIntStateWrite))) 97 case _ => None 98 } 99 100 val vfBusyTable = schdType match { 101 case VfScheduler() | MemScheduler() => Some(Module(new BusyTable(dispatch2Iq.numVfStateRead, wrapper.numVfStateWrite))) 102 case _ => None 103 } 104 105 dispatch2Iq.io match { case dp2iq => 106 dp2iq.redirect <> io.fromCtrlBlock.flush 107 dp2iq.in <> io.fromDispatch.uops 108 dp2iq.readIntState.foreach(_ <> intBusyTable.get.io.read) 109 dp2iq.readVfState.foreach(_ <> vfBusyTable.get.io.read) 110 } 111 112 intBusyTable match { 113 case Some(bt) => 114 bt.io.allocPregs.zip(io.fromDispatch.allocPregs).foreach { case (btAllocPregs, dpAllocPregs) => 115 btAllocPregs.valid := dpAllocPregs.isInt 116 btAllocPregs.bits := dpAllocPregs.preg 117 } 118 bt.io.wbPregs.zipWithIndex.foreach { case (wb, i) => 119 wb.valid := io.intWriteBack(i).wen && io.intWriteBack(i).intWen 120 wb.bits := io.intWriteBack(i).addr 121 } 122 case None => 123 } 124 125 vfBusyTable match { 126 case Some(bt) => 127 bt.io.allocPregs.zip(io.fromDispatch.allocPregs).foreach { case (btAllocPregs, dpAllocPregs) => 128 btAllocPregs.valid := dpAllocPregs.isFp 129 btAllocPregs.bits := dpAllocPregs.preg 130 } 131 bt.io.wbPregs.zipWithIndex.foreach { case (wb, i) => 132 wb.valid := io.vfWriteBack(i).wen && (io.vfWriteBack(i).fpWen || io.vfWriteBack(i).vecWen) 133 wb.bits := io.vfWriteBack(i).addr 134 } 135 case None => 136 } 137 138 val wakeupFromWBVec = Wire(Vec(params.numWakeupFromWB, ValidIO(new IssueQueueWakeUpBundle(params.pregIdxWidth)))) 139 val writeback = params.schdType match { 140 case IntScheduler() => io.intWriteBack 141 case MemScheduler() => io.intWriteBack ++ io.vfWriteBack 142 case VfScheduler() => io.vfWriteBack 143 case _ => Seq() 144 } 145 wakeupFromWBVec.zip(writeback).foreach { case (sink, source) => 146 sink.valid := source.wen 147 sink.bits.rfWen := source.intWen 148 sink.bits.fpWen := source.fpWen 149 sink.bits.vecWen := source.vecWen 150 sink.bits.pdest := source.addr 151 } 152 153 io.toDataPath.zipWithIndex.foreach { case (toDp, i) => 154 toDp <> issueQueues(i).io.deq 155 } 156} 157 158class SchedulerArithImp(override val wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 159 extends SchedulerImpBase(wrapper) 160 with HasXSParameter 161{ 162 println(s"[SchedulerArithImp] " + 163 s"has intBusyTable: ${intBusyTable.nonEmpty}, " + 164 s"has vfBusyTable: ${vfBusyTable.nonEmpty}") 165 166 issueQueues.zipWithIndex.foreach { case (iq, i) => 167 iq.io.flush <> io.fromCtrlBlock.flush 168 iq.io.enq <> dispatch2Iq.io.out(i) 169 iq.io.wakeup := wakeupFromWBVec 170 iq.io.deqResp.zipWithIndex.foreach { case (deqResp, j) => 171 deqResp.valid := iq.io.deq(j).valid && io.toDataPath(i)(j).ready 172 deqResp.bits.success := false.B 173 deqResp.bits.respType := RSFeedbackType.issueSuccess 174 deqResp.bits.addrOH := iq.io.deq(j).bits.addrOH 175 } 176 iq.io.og0Resp.zipWithIndex.foreach { case (og0Resp, j) => 177 og0Resp.valid := io.fromDataPath(i)(j).og0resp.valid 178 og0Resp.bits.success := false.B // Todo: remove it 179 og0Resp.bits.respType := io.fromDataPath(i)(j).og0resp.bits.respType 180 og0Resp.bits.addrOH := io.fromDataPath(i)(j).og0resp.bits.addrOH 181 } 182 iq.io.og1Resp.zipWithIndex.foreach { case (og1Resp, j) => 183 og1Resp.valid := io.fromDataPath(i)(j).og1resp.valid 184 og1Resp.bits.success := false.B 185 og1Resp.bits.respType := io.fromDataPath(i)(j).og1resp.bits.respType 186 og1Resp.bits.addrOH := io.fromDataPath(i)(j).og1resp.bits.addrOH 187 } 188 } 189 190 val iqJumpBundleVec: Seq[IssueQueueJumpBundle] = issueQueues.map { 191 case imp: IssueQueueIntImp => imp.io.enqJmp 192 case _ => None 193 }.filter(_.nonEmpty).flatMap(_.get) 194 println(s"[Scheduler] iqJumpBundleVec: ${iqJumpBundleVec}") 195 196 iqJumpBundleVec.zip(io.fromCtrlBlock.pcVec zip io.fromCtrlBlock.targetVec).foreach { case (iqJmp, (pc, target)) => 197 iqJmp.pc := pc 198 iqJmp.target := target 199 } 200} 201 202class SchedulerMemImp(override val wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 203 extends SchedulerImpBase(wrapper) 204 with HasXSParameter 205{ 206 println(s"[SchedulerMemImp] " + 207 s"has intBusyTable: ${intBusyTable.nonEmpty}, " + 208 s"has vfBusyTable: ${vfBusyTable.nonEmpty}") 209 210 val memAddrIQs = issueQueues.filter(iq => iq.params.StdCnt == 0) 211 val stAddrIQs = issueQueues.filter(iq => iq.params.StaCnt > 0) // included in memAddrIQs 212 val ldAddrIQs = issueQueues.filter(iq => iq.params.LduCnt > 0) 213 val stDataIQs = issueQueues.filter(iq => iq.params.StdCnt > 0) 214 require(memAddrIQs.nonEmpty && stDataIQs.nonEmpty) 215 216 issueQueues.zipWithIndex.foreach { case (iq, i) => 217 iq.io.deqResp.zipWithIndex.foreach { case (deqResp, j) => 218 deqResp.valid := iq.io.deq(j).valid && io.toDataPath(i)(j).ready 219 deqResp.bits.success := false.B 220 deqResp.bits.respType := RSFeedbackType.issueSuccess 221 deqResp.bits.addrOH := iq.io.deq(j).bits.addrOH 222 } 223 iq.io.og0Resp.zipWithIndex.foreach { case (og0Resp, j) => 224 og0Resp.valid := io.fromDataPath(i)(j).og0resp.valid 225 og0Resp.bits.success := false.B // Todo: remove it 226 og0Resp.bits.respType := io.fromDataPath(i)(j).og0resp.bits.respType 227 og0Resp.bits.addrOH := io.fromDataPath(i)(j).og0resp.bits.addrOH 228 } 229 iq.io.og1Resp.zipWithIndex.foreach { case (og1Resp, j) => 230 og1Resp.valid := io.fromDataPath(i)(j).og1resp.valid 231 og1Resp.bits.success := false.B 232 og1Resp.bits.respType := io.fromDataPath(i)(j).og1resp.bits.respType 233 og1Resp.bits.addrOH := io.fromDataPath(i)(j).og1resp.bits.addrOH 234 } 235 } 236 237 memAddrIQs.zipWithIndex.foreach { case (iq, i) => 238 iq.io.flush <> io.fromCtrlBlock.flush 239 iq.io.enq <> dispatch2Iq.io.out(i) 240 iq.io.wakeup := wakeupFromWBVec 241 } 242 243 ldAddrIQs.foreach { 244 case imp: IssueQueueMemAddrImp => imp.io.memIO.get.feedbackIO <> io.fromMem.get.ldaFeedback 245 case _ => 246 } 247 248 stAddrIQs.foreach { 249 case imp: IssueQueueMemAddrImp => imp.io.memIO.get.feedbackIO <> io.fromMem.get.staFeedback 250 case _ => 251 } 252 253 dispatch2Iq.io.out(1).zip(stAddrIQs(0).io.enq).zip(stDataIQs(0).io.enq).foreach{ case((di, staIQ), stdIQ) => 254 val isAllReady = staIQ.ready && stdIQ.ready 255 di.ready := isAllReady 256 staIQ.valid := di.valid && isAllReady 257 stdIQ.valid := di.valid && isAllReady 258 } 259 260 require(stAddrIQs.size == stDataIQs.size, s"number of store address IQs(${stAddrIQs.size}) " + 261 s"should be equal to number of data IQs(${stDataIQs})") 262 stDataIQs.zip(stAddrIQs).zipWithIndex.foreach { case ((stdIQ, staIQ), i) => 263 stdIQ.io.flush <> io.fromCtrlBlock.flush 264 265 stdIQ.io.enq.zip(staIQ.io.enq).foreach { case (stdIQEnq, staIQEnq) => 266 stdIQEnq.bits := staIQEnq.bits 267 // Store data reuses store addr src(1) in dispatch2iq 268 // [dispatch2iq] --src*------src*(0)--> [staIQ] 269 // \ 270 // ---src*(1)--> [stdIQ] 271 // Since the src(1) of sta is easier to get, stdIQEnq.bits.src*(0) is assigned to staIQEnq.bits.src*(1) 272 // instead of dispatch2Iq.io.out(x).bits.src*(1) 273 stdIQEnq.bits.srcState(0) := staIQEnq.bits.srcState(1) 274 stdIQEnq.bits.srcType(0) := staIQEnq.bits.srcType(1) 275 stdIQEnq.bits.psrc(0) := staIQEnq.bits.psrc(1) 276 stdIQEnq.bits.sqIdx := staIQEnq.bits.sqIdx 277 } 278 stdIQ.io.wakeup := wakeupFromWBVec 279 } 280 281 val lsqEnqCtrl = Module(new LsqEnqCtrl) 282 283 lsqEnqCtrl.io.redirect <> io.fromCtrlBlock.flush 284 lsqEnqCtrl.io.enq <> dispatch2Iq.io.enqLsqIO.get 285 lsqEnqCtrl.io.lcommit := io.fromMem.get.lcommit 286 lsqEnqCtrl.io.scommit := io.fromMem.get.scommit 287 lsqEnqCtrl.io.lqCancelCnt := io.fromMem.get.lqCancelCnt 288 lsqEnqCtrl.io.sqCancelCnt := io.fromMem.get.sqCancelCnt 289 io.memIO.get.lsqEnqIO <> lsqEnqCtrl.io.enqLsq 290} 291