1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import huancun._ 23import system.SoCParamsKey 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.dispatch.DispatchParameters 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler} 30import xiangshan.backend.regfile.{IntPregParams, PregParams, VfPregParams} 31import xiangshan.backend.BackendParams 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.prefetch._ 34import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 35import xiangshan.frontend.icache.ICacheParameters 36import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 37import xiangshan.frontend._ 38import xiangshan.frontend.icache.ICacheParameters 39 40import freechips.rocketchip.diplomacy.AddressSet 41import system.SoCParamsKey 42import huancun._ 43import huancun.debug._ 44import coupledL2._ 45import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 46 47import scala.math.min 48 49case object XSTileKey extends Field[Seq[XSCoreParameters]] 50 51case object XSCoreParamsKey extends Field[XSCoreParameters] 52 53case class XSCoreParameters 54( 55 HasPrefetch: Boolean = false, 56 HartId: Int = 0, 57 XLEN: Int = 64, 58 VLEN: Int = 128, 59 ELEN: Int = 64, 60 HasMExtension: Boolean = true, 61 HasCExtension: Boolean = true, 62 HasDiv: Boolean = true, 63 HasICache: Boolean = true, 64 HasDCache: Boolean = true, 65 AddrBits: Int = 64, 66 VAddrBits: Int = 39, 67 HasFPU: Boolean = true, 68 HasVPU: Boolean = true, 69 HasCustomCSRCacheOp: Boolean = true, 70 FetchWidth: Int = 8, 71 AsidLength: Int = 16, 72 EnableBPU: Boolean = true, 73 EnableBPD: Boolean = true, 74 EnableRAS: Boolean = true, 75 EnableLB: Boolean = false, 76 EnableLoop: Boolean = true, 77 EnableSC: Boolean = true, 78 EnbaleTlbDebug: Boolean = false, 79 EnableJal: Boolean = false, 80 EnableFauFTB: Boolean = true, 81 UbtbGHRLength: Int = 4, 82 // HistoryLength: Int = 512, 83 EnableGHistDiff: Boolean = true, 84 EnableCommitGHistDiff: Boolean = true, 85 UbtbSize: Int = 256, 86 FtbSize: Int = 2048, 87 RasSize: Int = 32, 88 CacheLineSize: Int = 512, 89 FtbWays: Int = 4, 90 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 91 // Sets Hist Tag 92 // Seq(( 2048, 2, 8), 93 // ( 2048, 9, 8), 94 // ( 2048, 13, 8), 95 // ( 2048, 20, 8), 96 // ( 2048, 26, 8), 97 // ( 2048, 44, 8), 98 // ( 2048, 73, 8), 99 // ( 2048, 256, 8)), 100 Seq(( 4096, 8, 8), 101 ( 4096, 13, 8), 102 ( 4096, 32, 8), 103 ( 4096, 119, 8)), 104 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 105 // Sets Hist Tag 106 Seq(( 256, 4, 9), 107 ( 256, 8, 9), 108 ( 512, 13, 9), 109 ( 512, 16, 9), 110 ( 512, 32, 9)), 111 SCNRows: Int = 512, 112 SCNTables: Int = 4, 113 SCCtrBits: Int = 6, 114 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 115 numBr: Int = 2, 116 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 117 ((resp_in: BranchPredictionResp, p: Parameters) => { 118 val ftb = Module(new FTB()(p)) 119 val ubtb =Module(new FauFTB()(p)) 120 // val bim = Module(new BIM()(p)) 121 val tage = Module(new Tage_SC()(p)) 122 val ras = Module(new RAS()(p)) 123 val ittage = Module(new ITTage()(p)) 124 val preds = Seq(ubtb, tage, ftb, ittage, ras) 125 preds.map(_.io := DontCare) 126 127 // ubtb.io.resp_in(0) := resp_in 128 // bim.io.resp_in(0) := ubtb.io.resp 129 // btb.io.resp_in(0) := bim.io.resp 130 // tage.io.resp_in(0) := btb.io.resp 131 // loop.io.resp_in(0) := tage.io.resp 132 ubtb.io.in.bits.resp_in(0) := resp_in 133 tage.io.in.bits.resp_in(0) := ubtb.io.out 134 ftb.io.in.bits.resp_in(0) := tage.io.out 135 ittage.io.in.bits.resp_in(0) := ftb.io.out 136 ras.io.in.bits.resp_in(0) := ittage.io.out 137 138 (preds, ras.io.out) 139 }), 140 IBufSize: Int = 48, 141 DecodeWidth: Int = 6, 142 RenameWidth: Int = 6, 143 CommitWidth: Int = 6, 144 MaxUopSize: Int = 65, 145 FtqSize: Int = 64, 146 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 147 IntLogicRegs: Int = 32, 148 FpLogicRegs: Int = 33, 149 VecLogicRegs: Int = 32 + 8 + 1, // 8: tmp, 1: vconfig 150 VCONFIG_IDX: Int = 40, 151 NRPhyRegs: Int = 192, 152 IntPhyRegs: Int = 192, 153 VfPhyRegs: Int = 192, 154 VirtualLoadQueueSize: Int = 80, 155 LoadQueueRARSize: Int = 80, 156 LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2. 157 RollbackGroupSize: Int = 8, 158 LoadQueueReplaySize: Int = 80, 159 LoadUncacheBufferSize: Int = 20, 160 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 161 StoreQueueSize: Int = 64, 162 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 163 StoreQueueForwardWithMask: Boolean = true, 164 VlsQueueSize: Int = 8, 165 RobSize: Int = 256, 166 RabSize: Int = 256, 167 dpParams: DispatchParameters = DispatchParameters( 168 IntDqSize = 16, 169 FpDqSize = 16, 170 LsDqSize = 16, 171 IntDqDeqWidth = 6, 172 FpDqDeqWidth = 6, 173 LsDqDeqWidth = 6, 174 ), 175 intPreg: PregParams = IntPregParams( 176 numEntries = 64, 177 numRead = 14, 178 numWrite = 8, 179 ), 180 vfPreg: VfPregParams = VfPregParams( 181 numEntries = 64, 182 numRead = 14, 183 numWrite = 8, 184 ), 185 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 186 LoadPipelineWidth: Int = 2, 187 StorePipelineWidth: Int = 2, 188 VecMemSrcInWidth: Int = 2, 189 VecMemInstWbWidth: Int = 1, 190 VecMemDispatchWidth: Int = 1, 191 StoreBufferSize: Int = 16, 192 StoreBufferThreshold: Int = 7, 193 EnsbufferWidth: Int = 2, 194 UncacheBufferSize: Int = 4, 195 EnableLoadToLoadForward: Boolean = true, 196 EnableFastForward: Boolean = false, 197 EnableLdVioCheckAfterReset: Boolean = true, 198 EnableSoftPrefetchAfterReset: Boolean = true, 199 EnableCacheErrorAfterReset: Boolean = true, 200 EnableDCacheWPU: Boolean = false, 201 EnableAccurateLoadError: Boolean = true, 202 EnableUncacheWriteOutstanding: Boolean = false, 203 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 204 ReSelectLen: Int = 7, // load replay queue replay select counter len 205 itlbParameters: TLBParameters = TLBParameters( 206 name = "itlb", 207 fetchi = true, 208 useDmode = false, 209 normalNWays = 32, 210 normalReplacer = Some("plru"), 211 superNWays = 4, 212 superReplacer = Some("plru") 213 ), 214 itlbPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 215 ipmpPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 216 ldtlbParameters: TLBParameters = TLBParameters( 217 name = "ldtlb", 218 normalNSets = 64, 219 normalNWays = 1, 220 normalAssociative = "sa", 221 normalReplacer = Some("setplru"), 222 superNWays = 16, 223 normalAsVictim = true, 224 outReplace = false, 225 partialStaticPMP = true, 226 outsideRecvFlush = true, 227 saveLevel = true 228 ), 229 sttlbParameters: TLBParameters = TLBParameters( 230 name = "sttlb", 231 normalNSets = 64, 232 normalNWays = 1, 233 normalAssociative = "sa", 234 normalReplacer = Some("setplru"), 235 superNWays = 16, 236 normalAsVictim = true, 237 outReplace = false, 238 partialStaticPMP = true, 239 outsideRecvFlush = true, 240 saveLevel = true 241 ), 242 pftlbParameters: TLBParameters = TLBParameters( 243 name = "pftlb", 244 normalNSets = 64, 245 normalNWays = 1, 246 normalAssociative = "sa", 247 normalReplacer = Some("setplru"), 248 superNWays = 16, 249 normalAsVictim = true, 250 outReplace = false, 251 partialStaticPMP = true, 252 outsideRecvFlush = true, 253 saveLevel = true 254 ), 255 refillBothTlb: Boolean = false, 256 btlbParameters: TLBParameters = TLBParameters( 257 name = "btlb", 258 normalNSets = 1, 259 normalNWays = 64, 260 superNWays = 4, 261 ), 262 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 263 NumPerfCounters: Int = 16, 264 icacheParameters: ICacheParameters = ICacheParameters( 265 tagECC = Some("parity"), 266 dataECC = Some("parity"), 267 replacer = Some("setplru"), 268 nMissEntries = 2, 269 nProbeEntries = 2, 270 nPrefetchEntries = 12, 271 nPrefBufferEntries = 64, 272 hasPrefetch = true, 273 ), 274 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 275 tagECC = Some("secded"), 276 dataECC = Some("secded"), 277 replacer = Some("setplru"), 278 nMissEntries = 16, 279 nProbeEntries = 8, 280 nReleaseEntries = 18 281 )), 282 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 283 name = "l2", 284 ways = 8, 285 sets = 1024, // default 512KB L2 286 prefetch = Some(coupledL2.prefetch.PrefetchReceiverParams()) 287 )), 288 L2NBanks: Int = 1, 289 usePTWRepeater: Boolean = false, 290 softTLB: Boolean = false, // dpi-c l1tlb debug only 291 softPTW: Boolean = false, // dpi-c l2tlb debug only 292 softPTWDelay: Int = 1 293){ 294 def vlWidth = log2Up(VLEN) + 1 295 296 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 297 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 298 299 def intSchdParams = { 300 implicit val schdType: SchedulerType = IntScheduler() 301 val pregBits = intPreg.addrWidth 302 val numRfRead = intPreg.numRead 303 val numRfWrite = intPreg.numWrite 304 SchdBlockParams(Seq( 305 IssueBlockParams(Seq( 306 ExeUnitParams(Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 2)), Seq(IntRD(1, 2)))), 307 ExeUnitParams(Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 1, 0)), Seq(Seq(IntRD(0, 1)), Seq(IntRD(1, 1)))), 308 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 309 IssueBlockParams(Seq( 310 ExeUnitParams(Seq(DivCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0)))), 311 ExeUnitParams(Seq(DivCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0)))), 312 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 313 IssueBlockParams(Seq( 314 ExeUnitParams(Seq(BrhCfg, JmpCfg, CsrCfg, FenceCfg), Seq(IntWB(port = 4, 0)), Seq(Seq(IntRD(2, 1)), Seq(IntRD(3, 1)))), 315 ExeUnitParams(Seq(BrhCfg), Seq(), Seq(Seq(IntRD(6, 1)), Seq(IntRD(4, 1)))), 316 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 317 IssueBlockParams(Seq( 318 ExeUnitParams(Seq(I2fCfg, VSetRiWiCfg, VSetRiWvfCfg), Seq(VecWB(port = 6, Int.MaxValue), IntWB(port = 7, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0)))), 319 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2) 320 ), 321 numPregs = intPreg.numEntries, 322 numRfReadWrite = Some((numRfRead, numRfWrite)), 323 numDeqOutside = 0, 324 schdType = schdType, 325 rfDataWidth = intPreg.dataCfg.dataWidth, 326 numUopIn = dpParams.IntDqDeqWidth, 327 ) 328 } 329 def vfSchdParams = { 330 implicit val schdType: SchedulerType = VfScheduler() 331 val pregBits = vfPreg.addrWidth 332 val numRfRead = vfPreg.numRead 333 val numRfWrite = vfPreg.numWrite 334 SchdBlockParams(Seq( 335 IssueBlockParams(Seq( 336 ExeUnitParams(Seq(VialuCfg), Seq(VecWB(port = 0, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))), 337 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 338 IssueBlockParams(Seq( 339 ExeUnitParams(Seq(FmacCfg), Seq(VecWB(port = 1, 0)), Seq(Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(VfRD(9, 0)))), 340 ExeUnitParams(Seq(F2fCfg, F2iCfg, FDivSqrtCfg, VSetRvfWvfCfg), Seq(VecWB(port = 2, 0), IntWB(port = 7, 0)), Seq(Seq(VfRD(10, 0)), Seq(VfRD(11, 0)))), 341 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 342 ), 343 numPregs = vfPreg.numEntries, 344 numRfReadWrite = Some((numRfRead, numRfWrite)), 345 numDeqOutside = 0, 346 schdType = schdType, 347 rfDataWidth = vfPreg.dataCfg.dataWidth, 348 numUopIn = dpParams.FpDqDeqWidth, 349 ) 350 } 351 def memSchdParams = { 352 implicit val schdType: SchedulerType = MemScheduler() 353 val pregBits = vfPreg.addrWidth max intPreg.addrWidth 354 val rfDataWidth = 64 355 356 SchdBlockParams(Seq( 357 IssueBlockParams(Seq( 358 ExeUnitParams(Seq(LduCfg), Seq(IntWB(5, 0), VecWB(4, 0)), Seq(Seq(IntRD(8, 0)))), 359 ExeUnitParams(Seq(LduCfg), Seq(IntWB(6, 0), VecWB(5, 0)), Seq(Seq(IntRD(9, 0)))), 360 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = 16, numEnq = 2), 361 IssueBlockParams(Seq( 362 ExeUnitParams(Seq(StaCfg, MouCfg), Seq(IntWB(5, 1)), Seq(Seq(IntRD(10, 0)))), 363 ExeUnitParams(Seq(StaCfg, MouCfg), Seq(IntWB(6, 1)), Seq(Seq(IntRD(11, 0)))), 364 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = 16, numEnq = 2), 365 IssueBlockParams(Seq( 366 ExeUnitParams(Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(12, 0), VfRD(12, 0)))), 367 ExeUnitParams(Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(13, 0), VfRD(13, 0)))), 368 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = 16, numEnq = 2), 369 IssueBlockParams(Seq( 370 ExeUnitParams(Seq(VlduCfg), Seq(VecWB(6, 0)), Seq(Seq(VfRD(0, 0)), Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)))), 371 ExeUnitParams(Seq(VlduCfg), Seq(VecWB(7, 0)), Seq(Seq(VfRD(5, 0)), Seq(VfRD(6, 0)), Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(VfRD(9, 0)))), 372 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = 16, numEnq = 2), 373 ), 374 numPregs = intPreg.numEntries max vfPreg.numEntries, 375 numRfReadWrite = None, 376 numDeqOutside = 0, 377 schdType = schdType, 378 rfDataWidth = rfDataWidth, 379 numUopIn = dpParams.LsDqDeqWidth, 380 ) 381 } 382 383 def backendParams: BackendParams = backend.BackendParams(Map( 384 IntScheduler() -> intSchdParams, 385 VfScheduler() -> vfSchdParams, 386 MemScheduler() -> memSchdParams, 387 ), Seq( 388 intPreg, 389 vfPreg, 390 )) 391} 392 393case object DebugOptionsKey extends Field[DebugOptions] 394 395case class DebugOptions 396( 397 FPGAPlatform: Boolean = false, 398 EnableDifftest: Boolean = false, 399 AlwaysBasicDiff: Boolean = true, 400 EnableDebug: Boolean = false, 401 EnablePerfDebug: Boolean = true, 402 UseDRAMSim: Boolean = false, 403 EnableConstantin: Boolean = false, 404 EnableTopDown: Boolean = false 405) 406 407trait HasXSParameter { 408 409 implicit val p: Parameters 410 411 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 412 413 val coreParams = p(XSCoreParamsKey) 414 val env = p(DebugOptionsKey) 415 416 val XLEN = coreParams.XLEN 417 val VLEN = coreParams.VLEN 418 val ELEN = coreParams.ELEN 419 val minFLen = 32 420 val fLen = 64 421 def xLen = XLEN 422 423 val HasMExtension = coreParams.HasMExtension 424 val HasCExtension = coreParams.HasCExtension 425 val HasDiv = coreParams.HasDiv 426 val HasIcache = coreParams.HasICache 427 val HasDcache = coreParams.HasDCache 428 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 429 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 430 val AsidLength = coreParams.AsidLength 431 val ReSelectLen = coreParams.ReSelectLen 432 val AddrBytes = AddrBits / 8 // unused 433 val DataBits = XLEN 434 val DataBytes = DataBits / 8 435 val HasFPU = coreParams.HasFPU 436 val HasVPU = coreParams.HasVPU 437 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 438 val FetchWidth = coreParams.FetchWidth 439 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 440 val EnableBPU = coreParams.EnableBPU 441 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 442 val EnableRAS = coreParams.EnableRAS 443 val EnableLB = coreParams.EnableLB 444 val EnableLoop = coreParams.EnableLoop 445 val EnableSC = coreParams.EnableSC 446 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 447 val HistoryLength = coreParams.HistoryLength 448 val EnableGHistDiff = coreParams.EnableGHistDiff 449 val EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 450 val UbtbGHRLength = coreParams.UbtbGHRLength 451 val UbtbSize = coreParams.UbtbSize 452 val EnableFauFTB = coreParams.EnableFauFTB 453 val FtbSize = coreParams.FtbSize 454 val FtbWays = coreParams.FtbWays 455 val RasSize = coreParams.RasSize 456 457 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 458 coreParams.branchPredictor(resp_in, p) 459 } 460 val numBr = coreParams.numBr 461 val TageTableInfos = coreParams.TageTableInfos 462 val TageBanks = coreParams.numBr 463 val SCNRows = coreParams.SCNRows 464 val SCCtrBits = coreParams.SCCtrBits 465 val SCHistLens = coreParams.SCHistLens 466 val SCNTables = coreParams.SCNTables 467 468 val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 469 case ((n, cb), h) => (n, cb, h) 470 } 471 val ITTageTableInfos = coreParams.ITTageTableInfos 472 type FoldedHistoryInfo = Tuple2[Int, Int] 473 val foldedGHistInfos = 474 (TageTableInfos.map{ case (nRows, h, t) => 475 if (h > 0) 476 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 477 else 478 Set[FoldedHistoryInfo]() 479 }.reduce(_++_).toSet ++ 480 SCTableInfos.map{ case (nRows, _, h) => 481 if (h > 0) 482 Set((h, min(log2Ceil(nRows/TageBanks), h))) 483 else 484 Set[FoldedHistoryInfo]() 485 }.reduce(_++_).toSet ++ 486 ITTageTableInfos.map{ case (nRows, h, t) => 487 if (h > 0) 488 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 489 else 490 Set[FoldedHistoryInfo]() 491 }.reduce(_++_) ++ 492 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 493 ).toList 494 495 496 497 val CacheLineSize = coreParams.CacheLineSize 498 val CacheLineHalfWord = CacheLineSize / 16 499 val ExtHistoryLength = HistoryLength + 64 500 val IBufSize = coreParams.IBufSize 501 val DecodeWidth = coreParams.DecodeWidth 502 val RenameWidth = coreParams.RenameWidth 503 val CommitWidth = coreParams.CommitWidth 504 val MaxUopSize = coreParams.MaxUopSize 505 val FtqSize = coreParams.FtqSize 506 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 507 val IntLogicRegs = coreParams.IntLogicRegs 508 val FpLogicRegs = coreParams.FpLogicRegs 509 val VecLogicRegs = coreParams.VecLogicRegs 510 val VCONFIG_IDX = coreParams.VCONFIG_IDX 511 val NRPhyRegs = coreParams.NRPhyRegs 512 val PhyRegIdxWidth = log2Up(NRPhyRegs) 513 val IntPhyRegs = coreParams.IntPhyRegs 514 val VfPhyRegs = coreParams.VfPhyRegs 515 val IntPregIdxWidth = log2Up(IntPhyRegs) 516 val VfPregIdxWidth = log2Up(VfPhyRegs) 517 val RobSize = coreParams.RobSize 518 val RabSize = coreParams.RabSize 519 val IntRefCounterWidth = log2Ceil(RobSize) 520 val VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 521 val LoadQueueRARSize = coreParams.LoadQueueRARSize 522 val LoadQueueRAWSize = coreParams.LoadQueueRAWSize 523 val RollbackGroupSize = coreParams.RollbackGroupSize 524 val LoadQueueReplaySize = coreParams.LoadQueueReplaySize 525 val LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 526 val LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 527 val StoreQueueSize = coreParams.StoreQueueSize 528 val StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 529 val StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 530 val VlsQueueSize = coreParams.VlsQueueSize 531 val dpParams = coreParams.dpParams 532 533 def backendParams: BackendParams = coreParams.backendParams 534 def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max 535 def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max 536 val LoadPipelineWidth = coreParams.LoadPipelineWidth 537 val StorePipelineWidth = coreParams.StorePipelineWidth 538 val VecMemSrcInWidth = coreParams.VecMemSrcInWidth 539 val VecMemInstWbWidth = coreParams.VecMemInstWbWidth 540 val VecMemDispatchWidth = coreParams.VecMemDispatchWidth 541 val StoreBufferSize = coreParams.StoreBufferSize 542 val StoreBufferThreshold = coreParams.StoreBufferThreshold 543 val EnsbufferWidth = coreParams.EnsbufferWidth 544 val UncacheBufferSize = coreParams.UncacheBufferSize 545 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 546 val EnableFastForward = coreParams.EnableFastForward 547 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 548 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 549 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 550 val EnableDCacheWPU = coreParams.EnableDCacheWPU 551 val EnableAccurateLoadError = coreParams.EnableAccurateLoadError 552 val EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 553 val asidLen = coreParams.MMUAsidLen 554 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 555 val refillBothTlb = coreParams.refillBothTlb 556 val itlbParams = coreParams.itlbParameters 557 val ldtlbParams = coreParams.ldtlbParameters 558 val sttlbParams = coreParams.sttlbParameters 559 val pftlbParams = coreParams.pftlbParameters 560 val btlbParams = coreParams.btlbParameters 561 val l2tlbParams = coreParams.l2tlbParameters 562 val NumPerfCounters = coreParams.NumPerfCounters 563 564 val instBytes = if (HasCExtension) 2 else 4 565 val instOffsetBits = log2Ceil(instBytes) 566 567 val icacheParameters = coreParams.icacheParameters 568 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 569 570 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 571 // for constrained LR/SC loop 572 val LRSCCycles = 64 573 // for lr storm 574 val LRSCBackOff = 8 575 576 // cache hierarchy configurations 577 val l1BusDataWidth = 256 578 579 // load violation predict 580 val ResetTimeMax2Pow = 20 //1078576 581 val ResetTimeMin2Pow = 10 //1024 582 // wait table parameters 583 val WaitTableSize = 1024 584 val MemPredPCWidth = log2Up(WaitTableSize) 585 val LWTUse2BitCounter = true 586 // store set parameters 587 val SSITSize = WaitTableSize 588 val LFSTSize = 32 589 val SSIDWidth = log2Up(LFSTSize) 590 val LFSTWidth = 4 591 val StoreSetEnable = true // LWT will be disabled if SS is enabled 592 val PCntIncrStep: Int = 6 593 val numPCntHc: Int = 25 594 val numPCntPtw: Int = 19 595 596 val numCSRPCntFrontend = 8 597 val numCSRPCntCtrl = 8 598 val numCSRPCntLsu = 8 599 val numCSRPCntHc = 5 600} 601