1// /*************************************************************************************** 2// * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3// * 4// * XiangShan is licensed under Mulan PSL v2. 5// * You can use this software according to the terms and conditions of the Mulan PSL v2. 6// * You may obtain a copy of Mulan PSL v2 at: 7// * http://license.coscl.org.cn/MulanPSL2 8// * 9// * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 10// * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 11// * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 12// * 13// * See the Mulan PSL v2 for more details. 14// ***************************************************************************************/ 15 16// package xiangshan.frontend 17 18// import chipsalliance.rocketchip.config.Parameters 19// import chisel3._ 20// import chisel3.util._ 21// import utils._ 22// import freechips.rocketchip.rocket.{RVCDecoder, ExpandedInstruction} 23// import xiangshan._ 24// import xiangshan.backend.decode.isa.predecode.PreDecodeInst 25// import xiangshan.cache._ 26 27// trait HasPdconst{ this: XSModule => 28// def isRVC(inst: UInt) = (inst(1,0) =/= 3.U) 29// def isLink(reg:UInt) = reg === 1.U || reg === 5.U 30// def brInfo(instr: UInt) = { 31// val brType::Nil = ListLookup(instr, List(BrType.notBr), PreDecodeInst.brTable) 32// val rd = Mux(isRVC(instr), instr(12), instr(11,7)) 33// val rs = Mux(isRVC(instr), Mux(brType === BrType.jal, 0.U, instr(11, 7)), instr(19, 15)) 34// val isCall = (brType === BrType.jal && !isRVC(instr) || brType === BrType.jalr) && isLink(rd) // Only for RV64 35// val isRet = brType === BrType.jalr && isLink(rs) && !isCall 36// List(brType, isCall, isRet) 37// } 38// } 39 40// object BrType { 41// def notBr = "b00".U 42// def branch = "b01".U 43// def jal = "b10".U 44// def jalr = "b11".U 45// def apply() = UInt(2.W) 46// } 47 48// object ExcType { //TODO:add exctype 49// def notExc = "b000".U 50// def apply() = UInt(3.W) 51// } 52 53// class PreDecodeInfo extends Bundle { // 8 bit 54// val isRVC = Bool() 55// val brType = UInt(2.W) 56// val isCall = Bool() 57// val isRet = Bool() 58// val excType = UInt(3.W) 59// def isBr = brType === BrType.branch 60// def isJal = brType === BrType.jal 61// def isJalr = brType === BrType.jalr 62// def notCFI = brType === BrType.notBr 63// } 64 65// class PreDecodeInfoForDebug(val usePerf: Boolean = true) extends Bundle { 66// val isRVC = if (usePerf) Bool() else UInt(0.W) 67// val brType = if (usePerf) UInt(2.W) else UInt(0.W) 68// val isCall = if (usePerf) Bool() else UInt(0.W) 69// val isRet = if (usePerf) Bool() else UInt(0.W) 70// val excType = if (usePerf) UInt(3.W) else UInt(0.W) 71// def isBr = brType === BrType.branch 72// def isJal = brType === BrType.jal 73// def isJalr = brType === BrType.jalr 74// def notCFI = brType === BrType.notBr 75// } 76 77// class PreDecodeResp(implicit p: Parameters) extends XSBundle with HasIFUConst { 78// val instrs = Vec(PredictWidth, UInt(32.W)) 79// val pc = Vec(PredictWidth, UInt(VAddrBits.W)) 80// val mask = UInt(PredictWidth.W) 81// // one for the first bank 82// val lastHalf = Bool() 83// val pd = Vec(PredictWidth, (new PreDecodeInfo)) 84// } 85 86// class PreDecode(implicit p: Parameters) extends XSModule with HasPdconst with HasIFUConst { 87// val io = IO(new Bundle() { 88// val in = Input(new ICacheResp) 89// val prev = Flipped(ValidIO(UInt(16.W))) 90// val prev_pc = Input(UInt(VAddrBits.W)) 91// val out = Output(new PreDecodeResp) 92// }) 93 94// val data = io.in.data 95// val mask = io.in.mask 96 97// val packetAlignedPC = packetAligned(io.in.pc) 98// val packetOffset = offsetInPacket(io.in.pc) 99 100// val firstValidIdx = packetOffset // io.prev.valid should only occur with firstValidIdx = 0 101// XSError(firstValidIdx =/= 0.U && io.prev.valid && HasCExtension.B, p"pc:${io.in.pc}, mask:${io.in.mask}, prevhalfInst valid occurs on unaligned fetch packet\n") 102 103// val instsMask = Wire(Vec(PredictWidth, Bool())) 104// val instsEndMask = Wire(Vec(PredictWidth, Bool())) 105 106// val rawInsts = if (HasCExtension) { 107// VecInit((0 until PredictWidth).map(i => if (i == PredictWidth-1) Cat(0.U(16.W), data(i*16+15, i*16)) 108// else data(i*16+31, i*16))) 109// } else { 110// VecInit((0 until PredictWidth).map(i => data(i*32+31, i*32))) 111// } 112 113// for (i <- 0 until PredictWidth) { 114// val inst = WireInit(rawInsts(i)) 115// val validStart = Wire(Bool()) // is the beginning of a valid inst 116// val validEnd = Wire(Bool()) // is the end of a valid inst 117 118// val isFirstInPacket = i.U === firstValidIdx 119// val isLastInPacket = (i == PredictWidth-1).B 120// val currentRVC = isRVC(inst) && HasCExtension.B 121 122// val lastIsValidEnd = (if (i == 0) { !io.prev.valid } else { instsEndMask(i-1) || isFirstInPacket }) || !HasCExtension.B 123 124// inst := (if (HasCExtension) 125// Mux(io.prev.valid && i.U === 0.U, 126// Cat(rawInsts(i)(15,0), io.prev.bits), 127// rawInsts(i)) 128// else 129// rawInsts(i)) 130 131// // when disable rvc, every 4 bytes should be an inst 132// validStart := lastIsValidEnd && !(isLastInPacket && !currentRVC) || !HasCExtension.B 133// validEnd := validStart && currentRVC || !validStart && !(isLastInPacket && !currentRVC) || !HasCExtension.B 134 135// val currentLastHalf = lastIsValidEnd && (isLastInPacket && !currentRVC) && HasCExtension.B 136 137// instsMask(i) := (if (i == 0) Mux(io.prev.valid, validEnd, validStart) else validStart) 138// instsEndMask(i) := validEnd 139 140// val brType::isCall::isRet::Nil = brInfo(inst) 141// io.out.pd(i).isRVC := currentRVC 142// io.out.pd(i).brType := brType 143// io.out.pd(i).isCall := isCall 144// io.out.pd(i).isRet := isRet 145// io.out.pd(i).excType := ExcType.notExc 146// io.out.instrs(i) := inst 147// io.out.pc(i) := Mux(io.prev.valid && HasCExtension.B && (i==0).B, io.prev_pc, Cat(packetIdx(io.in.pc), (i << instOffsetBits).U(log2Ceil(packetBytes).W))) 148 149// if (i == PredictWidth-1) { io.out.lastHalf := currentLastHalf } 150// } 151// io.out.mask := instsMask.asUInt & mask 152 153// for (i <- 0 until PredictWidth) { 154// XSDebug(true.B, 155// p"instr ${Hexadecimal(io.out.instrs(i))}, " + 156// p"mask ${Binary(instsMask(i))}, " + 157// p"endMask ${Binary(instsEndMask(i))}, " + 158// p"pc ${Hexadecimal(io.out.pc(i))}, " + 159// p"isRVC ${Binary(io.out.pd(i).isRVC)}, " + 160// p"brType ${Binary(io.out.pd(i).brType)}, " + 161// p"isRet ${Binary(io.out.pd(i).isRet)}, " + 162// p"isCall ${Binary(io.out.pd(i).isCall)}\n" 163// ) 164// } 165// } 166 167// class RVCExpander(implicit p: Parameters) extends XSModule { 168// val io = IO(new Bundle { 169// val in = Input(UInt(32.W)) 170// val out = Output(new ExpandedInstruction) 171// }) 172 173// if (HasCExtension) { 174// io.out := new RVCDecoder(io.in, XLEN).decode 175// } else { 176// io.out := new RVCDecoder(io.in, XLEN).passthrough 177// } 178// } 179