fix(PreDecode): fix fixedTaken for jalr (#4269)

This PR is a supplement to
https://github.com/OpenXiangShan/XiangShan/pull/4234, correctly setting
the ftqOffset when cfi is jalr.

fix(IFU): add range checking for instruction blocks containing jalr (#4234)

When there is a jalr instruction in the middle of an instruction block
but
the BPU fails to predict it, the IFU should a

fix(IFU): add range checking for instruction blocks containing jalr (#4234)

When there is a jalr instruction in the middle of an instruction block
but
the BPU fails to predict it, the IFU should adjust the length of the
instruction block to terminate at the jalr instruction.
However, the IFU currently does not check for this scenario, which may
result in the unintended execution of instructions following the jalr
that
should not have been executed. This PR fixed this issue.

show more ...

Frontend: modify the code related to configuration parameters (#3950)

fix(CSR,RVC): c.fp instrs should be illegal when fs is off (#3859)

* fix RVC floating-point inst raise EX_II in predecode when xstatus.fs
is off

Fix #3864

Update: https://github.com/OpenXiang

fix(CSR,RVC): c.fp instrs should be illegal when fs is off (#3859)

* fix RVC floating-point inst raise EX_II in predecode when xstatus.fs
is off

Fix #3864

Update: https://github.com/OpenXiangShan/rocket-chip/pull/20 is merged
and this PR is rebased, ready to review.

---------

Co-authored-by: sinceforYy <[email protected]>

show more ...

style(frontend): manually wrap some line (#3791)

style(Frontend): use scalafmt formatting frontend (#3370)

Format frontend according to the scalafmt file drafted in #3061.

Frontend: add RVC illegal instruction buffer

* Sstval requires instructions to be filled into stval

Trigger: refactor trigger information in pipeline. (#3403)

build: bump chisel 3.6.1, scala 2.13.14, mill 0.11.8, etc. (#3118)

IFU,ICache: clock gating optimization (#2957)


Co-authored-by: Liang Sen <[email protected]>

Merge remote-tracking branch 'upstream/master' into tmp-master

Ibuffer, PreDecode: consider valids for assertions (#2871)

Trigger: optimize trigger

* delete data trigger in frontend

* optimiza trigger comparison logic
co-author-by: Guokai Chen <[email protected]>

* delete frontendTiming & frontendChain

Trigger: optimize trigger

* delete data trigger in frontend

* optimiza trigger comparison logic
co-author-by: Guokai Chen <[email protected]>

* delete frontendTiming & frontendChain in TriggerCf

show more ...

Merge remote-tracking branch 'upstream/master' into backendq

Debug Module: cherry-pick debug module from nanhu

predecode: optimize frontend debug module size (#2424)

* frontendTrigger: optimize area

Frontend: delete unnecessary dontTouch in frontend (#2414)

Bump rocket-chip (#2353)

Bump rocket-chip (#2347)

Frontend: timing optimization (#2291)

Predecode delayed to f3 and use partial paralle valid generation logic
Remove CacheOp support in ICache

Frontend: fix jalTarget unintended value when no jalFault (#2203)

Predecode: fix unintended width cast (#2150)

Separate Utility submodule from XiangShan (#1861)

* misc: add utility submodule

* misc: adjust to new utility framework

* bump utility: revert resetgen

* bump huancun

<timing-opt> IFU: move expander from f2 to f3

<timing>: move targetFault to wb stage