1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.frontend 18 19import org.chipsalliance.cde.config.Parameters 20import freechips.rocketchip.rocket.{RVCDecoder, ExpandedInstruction} 21import chisel3.{util, _} 22import chisel3.util._ 23import utils._ 24import utility._ 25import xiangshan._ 26import xiangshan.frontend.icache._ 27import xiangshan.backend.decode.isa.predecode.PreDecodeInst 28import java.lang.reflect.Parameter 29import xiangshan.backend.fu.util.SdtrigExt 30 31trait HasPdConst extends HasXSParameter with HasICacheParameters with HasIFUConst{ 32 def isRVC(inst: UInt) = (inst(1,0) =/= 3.U) 33 def isLink(reg:UInt) = reg === 1.U || reg === 5.U 34 def brInfo(instr: UInt) = { 35 val brType::Nil = ListLookup(instr, List(BrType.notCFI), PreDecodeInst.brTable) 36 val rd = Mux(isRVC(instr), instr(12), instr(11,7)) 37 val rs = Mux(isRVC(instr), Mux(brType === BrType.jal, 0.U, instr(11, 7)), instr(19, 15)) 38 val isCall = (brType === BrType.jal && !isRVC(instr) || brType === BrType.jalr) && isLink(rd) // Only for RV64 39 val isRet = brType === BrType.jalr && isLink(rs) && !isCall 40 List(brType, isCall, isRet) 41 } 42 def jal_offset(inst: UInt, rvc: Bool): UInt = { 43 val rvc_offset = Cat(inst(12), inst(8), inst(10, 9), inst(6), inst(7), inst(2), inst(11), inst(5, 3), 0.U(1.W)) 44 val rvi_offset = Cat(inst(31), inst(19, 12), inst(20), inst(30, 21), 0.U(1.W)) 45 val max_width = rvi_offset.getWidth 46 SignExt(Mux(rvc, SignExt(rvc_offset, max_width), SignExt(rvi_offset, max_width)), XLEN) 47 } 48 def br_offset(inst: UInt, rvc: Bool): UInt = { 49 val rvc_offset = Cat(inst(12), inst(6, 5), inst(2), inst(11, 10), inst(4, 3), 0.U(1.W)) 50 val rvi_offset = Cat(inst(31), inst(7), inst(30, 25), inst(11, 8), 0.U(1.W)) 51 val max_width = rvi_offset.getWidth 52 SignExt(Mux(rvc, SignExt(rvc_offset, max_width), SignExt(rvi_offset, max_width)), XLEN) 53 } 54 55 def NOP = "h4501".U(16.W) 56} 57 58object BrType { 59 def notCFI = "b00".U 60 def branch = "b01".U 61 def jal = "b10".U 62 def jalr = "b11".U 63 def apply() = UInt(2.W) 64} 65 66object ExcType { //TODO:add exctype 67 def notExc = "b000".U 68 def apply() = UInt(3.W) 69} 70 71class PreDecodeInfo extends Bundle { // 8 bit 72 val valid = Bool() 73 val isRVC = Bool() 74 val brType = UInt(2.W) 75 val isCall = Bool() 76 val isRet = Bool() 77 //val excType = UInt(3.W) 78 def isBr = brType === BrType.branch 79 def isJal = brType === BrType.jal 80 def isJalr = brType === BrType.jalr 81 def notCFI = brType === BrType.notCFI 82} 83 84class PreDecodeResp(implicit p: Parameters) extends XSBundle with HasPdConst { 85 val pd = Vec(PredictWidth, new PreDecodeInfo) 86 val hasHalfValid = Vec(PredictWidth, Bool()) 87 //val expInstr = Vec(PredictWidth, UInt(32.W)) 88 val instr = Vec(PredictWidth, UInt(32.W)) 89 val jumpOffset = Vec(PredictWidth, UInt(XLEN.W)) 90// val hasLastHalf = Bool() 91 val triggered = Vec(PredictWidth, new TriggerCf) 92} 93 94class PreDecode(implicit p: Parameters) extends XSModule with HasPdConst{ 95 val io = IO(new Bundle() { 96 val in = Input(new IfuToPreDecode) 97 val out = Output(new PreDecodeResp) 98 }) 99 100 val data = io.in.data 101// val lastHalfMatch = io.in.lastHalfMatch 102 val validStart, validEnd = Wire(Vec(PredictWidth, Bool())) 103 val h_validStart, h_validEnd = Wire(Vec(PredictWidth, Bool())) 104 105 val validStart_half, validEnd_half = Wire(Vec(PredictWidth, Bool())) 106 val h_validStart_half, h_validEnd_half = Wire(Vec(PredictWidth, Bool())) 107 108 val validStart_halfPlus1, validEnd_halfPlus1 = Wire(Vec(PredictWidth, Bool())) 109 val h_validStart_halfPlus1, h_validEnd_halfPlus1 = Wire(Vec(PredictWidth, Bool())) 110 111 val validStart_diff, validEnd_diff = Wire(Vec(PredictWidth, Bool())) 112 val h_validStart_diff, h_validEnd_diff = Wire(Vec(PredictWidth, Bool())) 113 114 val currentIsRVC = Wire(Vec(PredictWidth, Bool())) 115 116 validStart_half.map(_ := false.B) 117 validEnd_half.map(_ := false.B) 118 h_validStart_half.map(_ := false.B) 119 h_validEnd_half.map(_ := false.B) 120 121 validStart_halfPlus1.map(_ := false.B) 122 validEnd_halfPlus1.map(_ := false.B) 123 h_validStart_halfPlus1.map(_ := false.B) 124 h_validEnd_halfPlus1.map(_ := false.B) 125 126 dontTouch(validStart_half) 127 dontTouch(validEnd_half) 128 dontTouch(h_validStart_half) 129 dontTouch(h_validEnd_half) 130 dontTouch(validStart_halfPlus1) 131 dontTouch(validEnd_halfPlus1) 132 dontTouch(h_validStart_halfPlus1) 133 dontTouch(h_validEnd_halfPlus1) 134 dontTouch(validStart_diff) 135 dontTouch(validEnd_diff) 136 dontTouch(h_validStart_diff) 137 dontTouch(h_validEnd_diff) 138 dontTouch(validStart) 139 dontTouch(validEnd) 140 dontTouch(h_validStart) 141 dontTouch(h_validEnd) 142 143 val rawInsts = if (HasCExtension) VecInit((0 until PredictWidth).map(i => Cat(data(i+1), data(i)))) 144 else VecInit((0 until PredictWidth).map(i => data(i))) 145 146 for (i <- 0 until PredictWidth) { 147 val inst = WireInit(rawInsts(i)) 148 //val expander = Module(new RVCExpander) 149 currentIsRVC(i) := isRVC(inst) 150 val currentPC = io.in.pc(i) 151 //expander.io.in := inst 152 153 val brType::isCall::isRet::Nil = brInfo(inst) 154 val jalOffset = jal_offset(inst, currentIsRVC(i)) 155 val brOffset = br_offset(inst, currentIsRVC(i)) 156 157 io.out.hasHalfValid(i) := h_validStart(i) 158 159 io.out.triggered(i) := DontCare//VecInit(Seq.fill(10)(false.B)) 160 161 162 io.out.pd(i).valid := validStart(i) 163 io.out.pd(i).isRVC := currentIsRVC(i) 164 165 // for diff purpose only 166 io.out.pd(i).brType := brType 167 io.out.pd(i).isCall := isCall 168 io.out.pd(i).isRet := isRet 169 170 //io.out.expInstr(i) := expander.io.out.bits 171 io.out.instr(i) :=inst 172 io.out.jumpOffset(i) := Mux(io.out.pd(i).isBr, brOffset, jalOffset) 173 } 174 175 // the first half is always reliable 176 for (i <- 0 until PredictWidth / 2) { 177 val lastIsValidEnd = if (i == 0) { true.B } else { validEnd(i-1) || !HasCExtension.B } 178 validStart(i) := (lastIsValidEnd || !HasCExtension.B) 179 validEnd(i) := validStart(i) && currentIsRVC(i) || !validStart(i) || !HasCExtension.B 180 181 //prepared for last half match 182 val h_lastIsValidEnd = if (i == 0) { false.B } else { h_validEnd(i-1) || !HasCExtension.B } 183 h_validStart(i) := (h_lastIsValidEnd || !HasCExtension.B) 184 h_validEnd(i) := h_validStart(i) && currentIsRVC(i) || !h_validStart(i) || !HasCExtension.B 185 } 186 187 for (i <- 0 until PredictWidth) { 188 val lastIsValidEnd = if (i == 0) { true.B } else { validEnd_diff(i-1) || !HasCExtension.B } 189 validStart_diff(i) := (lastIsValidEnd || !HasCExtension.B) 190 validEnd_diff(i) := validStart_diff(i) && currentIsRVC(i) || !validStart_diff(i) || !HasCExtension.B 191 192 //prepared for last half match 193 val h_lastIsValidEnd = if (i == 0) { false.B } else { h_validEnd_diff(i-1) || !HasCExtension.B } 194 h_validStart_diff(i) := (h_lastIsValidEnd || !HasCExtension.B) 195 h_validEnd_diff(i) := h_validStart_diff(i) && currentIsRVC(i) || !h_validStart_diff(i) || !HasCExtension.B 196 } 197 198 // assume PredictWidth / 2 is a valid start 199 for (i <- PredictWidth / 2 until PredictWidth) { 200 val lastIsValidEnd = if (i == PredictWidth / 2) { true.B } else { validEnd_half(i-1) || !HasCExtension.B } 201 validStart_half(i) := (lastIsValidEnd || !HasCExtension.B) 202 validEnd_half(i) := validStart_half(i) && currentIsRVC(i) || !validStart_half(i) || !HasCExtension.B 203 204 //prepared for last half match 205 val h_lastIsValidEnd = if (i == PredictWidth / 2) { true.B } else { h_validEnd_half(i-1) || !HasCExtension.B } 206 h_validStart_half(i) := (h_lastIsValidEnd || !HasCExtension.B) 207 h_validEnd_half(i) := h_validStart_half(i) && currentIsRVC(i) || !h_validStart_half(i) || !HasCExtension.B 208 } 209 210 // assume PredictWidth / 2 + 1 is a valid start (and PredictWidth / 2 is last half of RVI) 211 for (i <- PredictWidth / 2 + 1 until PredictWidth) { 212 val lastIsValidEnd = if (i == PredictWidth / 2 + 1) { true.B } else { validEnd_halfPlus1(i-1) || !HasCExtension.B } 213 validStart_halfPlus1(i) := (lastIsValidEnd || !HasCExtension.B) 214 validEnd_halfPlus1(i) := validStart_halfPlus1(i) && currentIsRVC(i) || !validStart_halfPlus1(i) || !HasCExtension.B 215 216 //prepared for last half match 217 val h_lastIsValidEnd = if (i == PredictWidth / 2 + 1) { true.B } else { h_validEnd_halfPlus1(i-1) || !HasCExtension.B } 218 h_validStart_halfPlus1(i) := (h_lastIsValidEnd || !HasCExtension.B) 219 h_validEnd_halfPlus1(i) := h_validStart_halfPlus1(i) && currentIsRVC(i) || !h_validStart_halfPlus1(i) || !HasCExtension.B 220 } 221 validStart_halfPlus1(PredictWidth / 2) := false.B // could be true but when true we select half, not halfPlus1 222 validEnd_halfPlus1(PredictWidth / 2) := true.B 223 224 // assume h_PredictWidth / 2 is an end 225 h_validStart_halfPlus1(PredictWidth / 2) := false.B // could be true but when true we select half, not halfPlus1 226 h_validEnd_halfPlus1(PredictWidth / 2) := true.B 227 228 // if PredictWidth / 2 - 1 is a valid end, PredictWidth / 2 is a valid start 229 for (i <- PredictWidth / 2 until PredictWidth) { 230 validStart(i) := Mux(validEnd(PredictWidth / 2 - 1), validStart_half(i), validStart_halfPlus1(i)) 231 validEnd(i) := Mux(validEnd(PredictWidth / 2 - 1), validEnd_half(i), validEnd_halfPlus1(i)) 232 h_validStart(i) := Mux(h_validEnd(PredictWidth / 2 - 1), h_validStart_half(i), h_validStart_halfPlus1(i)) 233 h_validEnd(i) := Mux(h_validEnd(PredictWidth / 2 - 1), h_validEnd_half(i), h_validEnd_halfPlus1(i)) 234 } 235 236 val validStartMismatch = Wire(Bool()) 237 val validEndMismatch = Wire(Bool()) 238 val validH_ValidStartMismatch = Wire(Bool()) 239 val validH_ValidEndMismatch = Wire(Bool()) 240 241 validStartMismatch := validStart.zip(validStart_diff).map{case(a,b) => a =/= b}.reduce(_||_) 242 validEndMismatch := validEnd.zip(validEnd_diff).map{case(a,b) => a =/= b}.reduce(_||_) 243 validH_ValidStartMismatch := h_validStart.zip(h_validStart_diff).map{case(a,b) => a =/= b}.reduce(_||_) 244 validH_ValidEndMismatch := h_validEnd.zip(h_validEnd_diff).map{case(a,b) => a =/= b}.reduce(_||_) 245 246 XSError(validStartMismatch, p"validStart mismatch\n") 247 XSError(validEndMismatch, p"validEnd mismatch\n") 248 XSError(validH_ValidStartMismatch, p"h_validStart mismatch\n") 249 XSError(validH_ValidEndMismatch, p"h_validEnd mismatch\n") 250 251// io.out.hasLastHalf := !io.out.pd(PredictWidth - 1).isRVC && io.out.pd(PredictWidth - 1).valid 252 253 for (i <- 0 until PredictWidth) { 254 XSDebug(true.B, 255 p"instr ${Hexadecimal(io.out.instr(i))}, " + 256 p"validStart ${Binary(validStart(i))}, " + 257 p"validEnd ${Binary(validEnd(i))}, " + 258 p"isRVC ${Binary(io.out.pd(i).isRVC)}, " + 259 p"brType ${Binary(io.out.pd(i).brType)}, " + 260 p"isRet ${Binary(io.out.pd(i).isRet)}, " + 261 p"isCall ${Binary(io.out.pd(i).isCall)}\n" 262 ) 263 } 264} 265 266class IfuToF3PreDecode(implicit p: Parameters) extends XSBundle with HasPdConst { 267 val instr = Vec(PredictWidth, UInt(32.W)) 268} 269 270class F3PreDecodeResp(implicit p: Parameters) extends XSBundle with HasPdConst { 271 val pd = Vec(PredictWidth, new PreDecodeInfo) 272} 273class F3Predecoder(implicit p: Parameters) extends XSModule with HasPdConst { 274 val io = IO(new Bundle() { 275 val in = Input(new IfuToF3PreDecode) 276 val out = Output(new F3PreDecodeResp) 277 }) 278 io.out.pd.zipWithIndex.map{ case (pd,i) => 279 pd.valid := DontCare 280 pd.isRVC := DontCare 281 pd.brType := brInfo(io.in.instr(i))(0) 282 pd.isCall := brInfo(io.in.instr(i))(1) 283 pd.isRet := brInfo(io.in.instr(i))(2) 284 } 285 286} 287 288class RVCExpander(implicit p: Parameters) extends XSModule { 289 val io = IO(new Bundle { 290 val in = Input(UInt(32.W)) 291 val out = Output(new ExpandedInstruction) 292 }) 293 294 if (HasCExtension) { 295 io.out := new RVCDecoder(io.in, XLEN, useAddiForMv = true).decode 296 } else { 297 io.out := new RVCDecoder(io.in, XLEN, useAddiForMv = true).passthrough 298 } 299} 300 301/* --------------------------------------------------------------------- 302 * Predict result check 303 * 304 * --------------------------------------------------------------------- 305 */ 306 307object FaultType { 308 def noFault = "b000".U 309 def jalFault = "b001".U //not CFI taken or invalid instruction taken 310 def retFault = "b010".U //not CFI taken or invalid instruction taken 311 def targetFault = "b011".U 312 def notCFIFault = "b100".U //not CFI taken or invalid instruction taken 313 def invalidTaken = "b101".U 314 def apply() = UInt(3.W) 315} 316 317class CheckInfo extends Bundle { // 8 bit 318 val value = UInt(3.W) 319 def isjalFault = value === FaultType.jalFault 320 def isRetFault = value === FaultType.retFault 321 def istargetFault = value === FaultType.targetFault 322 def invalidTakenFault = value === FaultType.invalidTaken 323 def notCFIFault = value === FaultType.notCFIFault 324} 325 326class PredCheckerResp(implicit p: Parameters) extends XSBundle with HasPdConst { 327 //to Ibuffer write port (stage 1) 328 val stage1Out = new Bundle{ 329 val fixedRange = Vec(PredictWidth, Bool()) 330 val fixedTaken = Vec(PredictWidth, Bool()) 331 } 332 //to Ftq write back port (stage 2) 333 val stage2Out = new Bundle{ 334 val fixedTarget = Vec(PredictWidth, UInt(VAddrBits.W)) 335 val jalTarget = Vec(PredictWidth, UInt(VAddrBits.W)) 336 val fixedMissPred = Vec(PredictWidth, Bool()) 337 val faultType = Vec(PredictWidth, new CheckInfo) 338 } 339} 340 341 342class PredChecker(implicit p: Parameters) extends XSModule with HasPdConst { 343 val io = IO( new Bundle{ 344 val in = Input(new IfuToPredChecker) 345 val out = Output(new PredCheckerResp) 346 }) 347 348 val (takenIdx, predTaken) = (io.in.ftqOffset.bits, io.in.ftqOffset.valid) 349 val predTarget = (io.in.target) 350 val (instrRange, instrValid) = (io.in.instrRange, io.in.instrValid) 351 val (pds, pc, jumpOffset) = (io.in.pds, io.in.pc, io.in.jumpOffset) 352 353 val jalFaultVec, retFaultVec, targetFault, notCFITaken, invalidTaken = Wire(Vec(PredictWidth, Bool())) 354 355 /** remask fault may appear together with other faults, but other faults are exclusive 356 * so other f ault mast use fixed mask to keep only one fault would be found and redirect to Ftq 357 * we first detecct remask fault and then use fixedRange to do second check 358 **/ 359 360 //Stage 1: detect remask fault 361 /** first check: remask Fault */ 362 jalFaultVec := VecInit(pds.zipWithIndex.map{case(pd, i) => pd.isJal && instrRange(i) && instrValid(i) && (takenIdx > i.U && predTaken || !predTaken) }) 363 retFaultVec := VecInit(pds.zipWithIndex.map{case(pd, i) => pd.isRet && instrRange(i) && instrValid(i) && (takenIdx > i.U && predTaken || !predTaken) }) 364 val remaskFault = VecInit((0 until PredictWidth).map(i => jalFaultVec(i) || retFaultVec(i))) 365 val remaskIdx = ParallelPriorityEncoder(remaskFault.asUInt) 366 val needRemask = ParallelOR(remaskFault) 367 val fixedRange = instrRange.asUInt & (Fill(PredictWidth, !needRemask) | Fill(PredictWidth, 1.U(1.W)) >> ~remaskIdx) 368 369 io.out.stage1Out.fixedRange := fixedRange.asTypeOf((Vec(PredictWidth, Bool()))) 370 371 io.out.stage1Out.fixedTaken := VecInit(pds.zipWithIndex.map{case(pd, i) => instrValid (i) && fixedRange(i) && (pd.isRet || pd.isJal || takenIdx === i.U && predTaken && !pd.notCFI) }) 372 373 /** second check: faulse prediction fault and target fault */ 374 notCFITaken := VecInit(pds.zipWithIndex.map{case(pd, i) => fixedRange(i) && instrValid(i) && i.U === takenIdx && pd.notCFI && predTaken }) 375 invalidTaken := VecInit(pds.zipWithIndex.map{case(pd, i) => fixedRange(i) && !instrValid(i) && i.U === takenIdx && predTaken }) 376 377 val jumpTargets = VecInit(pds.zipWithIndex.map{case(pd,i) => (pc(i) + jumpOffset(i)).asTypeOf(UInt(VAddrBits.W))}) 378 val seqTargets = VecInit((0 until PredictWidth).map(i => pc(i) + Mux(pds(i).isRVC || !instrValid(i), 2.U, 4.U ) )) 379 380 //Stage 2: detect target fault 381 /** target calculation: in the next stage */ 382 val fixedRangeNext = RegNext(fixedRange) 383 val instrValidNext = RegNext(instrValid) 384 val takenIdxNext = RegNext(takenIdx) 385 val predTakenNext = RegNext(predTaken) 386 val predTargetNext = RegNext(predTarget) 387 val jumpTargetsNext = RegNext(jumpTargets) 388 val seqTargetsNext = RegNext(seqTargets) 389 val pdsNext = RegNext(pds) 390 val jalFaultVecNext = RegNext(jalFaultVec) 391 val retFaultVecNext = RegNext(retFaultVec) 392 val notCFITakenNext = RegNext(notCFITaken) 393 val invalidTakenNext = RegNext(invalidTaken) 394 395 targetFault := VecInit(pdsNext.zipWithIndex.map{case(pd,i) => fixedRangeNext(i) && instrValidNext(i) && (pd.isJal || pd.isBr) && takenIdxNext === i.U && predTakenNext && (predTargetNext =/= jumpTargetsNext(i))}) 396 397 398 io.out.stage2Out.faultType.zipWithIndex.map{case(faultType, i) => faultType.value := Mux(jalFaultVecNext(i) , FaultType.jalFault , 399 Mux(retFaultVecNext(i), FaultType.retFault , 400 Mux(targetFault(i), FaultType.targetFault , 401 Mux(notCFITakenNext(i) , FaultType.notCFIFault, 402 Mux(invalidTakenNext(i), FaultType.invalidTaken, FaultType.noFault)))))} 403 404 io.out.stage2Out.fixedMissPred.zipWithIndex.map{case(missPred, i ) => missPred := jalFaultVecNext(i) || retFaultVecNext(i) || notCFITakenNext(i) || invalidTakenNext(i) || targetFault(i)} 405 io.out.stage2Out.fixedTarget.zipWithIndex.map{case(target, i) => target := Mux(jalFaultVecNext(i) || targetFault(i), jumpTargetsNext(i), seqTargetsNext(i) )} 406 io.out.stage2Out.jalTarget.zipWithIndex.map{case(target, i) => target := jumpTargetsNext(i) } 407 408} 409 410class FrontendTrigger(implicit p: Parameters) extends XSModule with SdtrigExt { 411 val io = IO(new Bundle(){ 412 val frontendTrigger = Input(new FrontendTdataDistributeIO) 413 val triggered = Output(Vec(PredictWidth, new TriggerCf)) 414 415 val pds = Input(Vec(PredictWidth, new PreDecodeInfo)) 416 val pc = Input(Vec(PredictWidth, UInt(VAddrBits.W))) 417 val data = if(HasCExtension) Input(Vec(PredictWidth + 1, UInt(16.W))) 418 else Input(Vec(PredictWidth, UInt(32.W))) 419 }) 420 421 val data = io.data 422 423 val rawInsts = if (HasCExtension) VecInit((0 until PredictWidth).map(i => Cat(data(i+1), data(i)))) 424 else VecInit((0 until PredictWidth).map(i => data(i))) 425 426 val tdata = RegInit(VecInit(Seq.fill(TriggerNum)(0.U.asTypeOf(new MatchTriggerIO)))) 427 when(io.frontendTrigger.tUpdate.valid) { 428 tdata(io.frontendTrigger.tUpdate.bits.addr) := io.frontendTrigger.tUpdate.bits.tdata 429 } 430 val triggerEnableVec = RegInit(VecInit(Seq.fill(TriggerNum)(false.B))) // From CSR, controlled by priv mode, etc. 431 triggerEnableVec := io.frontendTrigger.tEnableVec 432 XSDebug(triggerEnableVec.asUInt.orR, "Debug Mode: At least one frontend trigger is enabled\n") 433 434 val triggerTimingVec = VecInit(tdata.map(_.timing)) 435 val triggerChainVec = VecInit(tdata.map(_.chain)) 436 437 for (i <- 0 until TriggerNum) { PrintTriggerInfo(triggerEnableVec(i), tdata(i)) } 438 439 for (i <- 0 until PredictWidth) { 440 val currentPC = io.pc(i) 441 val currentIsRVC = io.pds(i).isRVC 442 val inst = WireInit(rawInsts(i)) 443 val triggerHitVec = Wire(Vec(TriggerNum, Bool())) 444 val triggerCanFireVec = Wire(Vec(TriggerNum, Bool())) 445 446 for (j <- 0 until TriggerNum) { 447 triggerHitVec(j) := Mux( 448 tdata(j).select, 449 TriggerCmp(Mux(currentIsRVC, inst(15, 0), inst), tdata(j).tdata2, tdata(j).matchType, triggerEnableVec(j)), 450 TriggerCmp(currentPC, tdata(j).tdata2, tdata(j).matchType, triggerEnableVec(j)) 451 ) 452 } 453 454 TriggerCheckCanFire(TriggerNum, triggerCanFireVec, triggerHitVec, triggerTimingVec, triggerChainVec) 455 456 // only hit, no matter fire or not 457 io.triggered(i).frontendHit := triggerHitVec 458 // can fire, exception will be handled at rob enq 459 io.triggered(i).frontendCanFire := triggerCanFireVec 460 io.triggered(i).frontendTiming := triggerTimingVec.zip(triggerEnableVec).map{ case(timing, en) => timing && en} 461 io.triggered(i).frontendChain := triggerChainVec.zip(triggerEnableVec).map{ case(chain, en) => chain && en} 462 XSDebug(io.triggered(i).getFrontendCanFire, p"Debug Mode: Predecode Inst No. ${i} has trigger fire vec ${io.triggered(i).frontendCanFire}\n") 463 } 464 io.triggered.foreach(_.backendCanFire := VecInit(Seq.fill(TriggerNum)(false.B))) 465 io.triggered.foreach(_.backendHit := VecInit(Seq.fill(TriggerNum)(false.B))) 466} 467