1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.frontend 18 19import org.chipsalliance.cde.config.Parameters 20import freechips.rocketchip.rocket.{RVCDecoder, ExpandedInstruction} 21import chisel3.{util, _} 22import chisel3.util._ 23import utils._ 24import utility._ 25import xiangshan._ 26import xiangshan.frontend.icache._ 27import xiangshan.backend.decode.isa.predecode.PreDecodeInst 28import xiangshan.backend.fu.NewCSR.TriggerUtil 29import java.lang.reflect.Parameter 30import xiangshan.backend.fu.util.SdtrigExt 31 32trait HasPdConst extends HasXSParameter with HasICacheParameters with HasIFUConst{ 33 def isRVC(inst: UInt) = (inst(1,0) =/= 3.U) 34 def isLink(reg:UInt) = reg === 1.U || reg === 5.U 35 def brInfo(instr: UInt) = { 36 val brType::Nil = ListLookup(instr, List(BrType.notCFI), PreDecodeInst.brTable) 37 val rd = Mux(isRVC(instr), instr(12), instr(11,7)) 38 val rs = Mux(isRVC(instr), Mux(brType === BrType.jal, 0.U, instr(11, 7)), instr(19, 15)) 39 val isCall = (brType === BrType.jal && !isRVC(instr) || brType === BrType.jalr) && isLink(rd) // Only for RV64 40 val isRet = brType === BrType.jalr && isLink(rs) && !isCall 41 List(brType, isCall, isRet) 42 } 43 def jal_offset(inst: UInt, rvc: Bool): UInt = { 44 val rvc_offset = Cat(inst(12), inst(8), inst(10, 9), inst(6), inst(7), inst(2), inst(11), inst(5, 3), 0.U(1.W)) 45 val rvi_offset = Cat(inst(31), inst(19, 12), inst(20), inst(30, 21), 0.U(1.W)) 46 val max_width = rvi_offset.getWidth 47 SignExt(Mux(rvc, SignExt(rvc_offset, max_width), SignExt(rvi_offset, max_width)), XLEN) 48 } 49 def br_offset(inst: UInt, rvc: Bool): UInt = { 50 val rvc_offset = Cat(inst(12), inst(6, 5), inst(2), inst(11, 10), inst(4, 3), 0.U(1.W)) 51 val rvi_offset = Cat(inst(31), inst(7), inst(30, 25), inst(11, 8), 0.U(1.W)) 52 val max_width = rvi_offset.getWidth 53 SignExt(Mux(rvc, SignExt(rvc_offset, max_width), SignExt(rvi_offset, max_width)), XLEN) 54 } 55 56 def NOP = "h4501".U(16.W) 57} 58 59object BrType { 60 def notCFI = "b00".U 61 def branch = "b01".U 62 def jal = "b10".U 63 def jalr = "b11".U 64 def apply() = UInt(2.W) 65} 66 67object ExcType { //TODO:add exctype 68 def notExc = "b000".U 69 def apply() = UInt(3.W) 70} 71 72class PreDecodeInfo extends Bundle { // 8 bit 73 val valid = Bool() 74 val isRVC = Bool() 75 val brType = UInt(2.W) 76 val isCall = Bool() 77 val isRet = Bool() 78 //val excType = UInt(3.W) 79 def isBr = brType === BrType.branch 80 def isJal = brType === BrType.jal 81 def isJalr = brType === BrType.jalr 82 def notCFI = brType === BrType.notCFI 83} 84 85class PreDecodeResp(implicit p: Parameters) extends XSBundle with HasPdConst { 86 val pd = Vec(PredictWidth, new PreDecodeInfo) 87 val hasHalfValid = Vec(PredictWidth, Bool()) 88 //val expInstr = Vec(PredictWidth, UInt(32.W)) 89 val instr = Vec(PredictWidth, UInt(32.W)) 90 val jumpOffset = Vec(PredictWidth, UInt(XLEN.W)) 91// val hasLastHalf = Bool() 92 val triggered = Vec(PredictWidth, TriggerAction()) 93} 94 95class PreDecode(implicit p: Parameters) extends XSModule with HasPdConst{ 96 val io = IO(new Bundle() { 97 val in = Input(ValidIO(new IfuToPreDecode)) 98 val out = Output(new PreDecodeResp) 99 }) 100 101 val data = io.in.bits.data 102// val lastHalfMatch = io.in.lastHalfMatch 103 val validStart, validEnd = Wire(Vec(PredictWidth, Bool())) 104 val h_validStart, h_validEnd = Wire(Vec(PredictWidth, Bool())) 105 106 val validStart_half, validEnd_half = Wire(Vec(PredictWidth, Bool())) 107 val h_validStart_half, h_validEnd_half = Wire(Vec(PredictWidth, Bool())) 108 109 val validStart_halfPlus1, validEnd_halfPlus1 = Wire(Vec(PredictWidth, Bool())) 110 val h_validStart_halfPlus1, h_validEnd_halfPlus1 = Wire(Vec(PredictWidth, Bool())) 111 112 val validStart_diff, validEnd_diff = Wire(Vec(PredictWidth, Bool())) 113 val h_validStart_diff, h_validEnd_diff = Wire(Vec(PredictWidth, Bool())) 114 115 val currentIsRVC = Wire(Vec(PredictWidth, Bool())) 116 117 validStart_half.map(_ := false.B) 118 validEnd_half.map(_ := false.B) 119 h_validStart_half.map(_ := false.B) 120 h_validEnd_half.map(_ := false.B) 121 122 validStart_halfPlus1.map(_ := false.B) 123 validEnd_halfPlus1.map(_ := false.B) 124 h_validStart_halfPlus1.map(_ := false.B) 125 h_validEnd_halfPlus1.map(_ := false.B) 126 127 val rawInsts = if (HasCExtension) VecInit((0 until PredictWidth).map(i => Cat(data(i+1), data(i)))) 128 else VecInit((0 until PredictWidth).map(i => data(i))) 129 130 for (i <- 0 until PredictWidth) { 131 val inst = WireInit(rawInsts(i)) 132 //val expander = Module(new RVCExpander) 133 currentIsRVC(i) := isRVC(inst) 134 val currentPC = io.in.bits.pc(i) 135 //expander.io.in := inst 136 137 val brType::isCall::isRet::Nil = brInfo(inst) 138 val jalOffset = jal_offset(inst, currentIsRVC(i)) 139 val brOffset = br_offset(inst, currentIsRVC(i)) 140 141 io.out.hasHalfValid(i) := h_validStart(i) 142 143 io.out.triggered(i) := DontCare//VecInit(Seq.fill(10)(false.B)) 144 145 146 io.out.pd(i).valid := validStart(i) 147 io.out.pd(i).isRVC := currentIsRVC(i) 148 149 // for diff purpose only 150 io.out.pd(i).brType := brType 151 io.out.pd(i).isCall := isCall 152 io.out.pd(i).isRet := isRet 153 154 //io.out.expInstr(i) := expander.io.out.bits 155 io.out.instr(i) :=inst 156 io.out.jumpOffset(i) := Mux(io.out.pd(i).isBr, brOffset, jalOffset) 157 } 158 159 // the first half is always reliable 160 for (i <- 0 until PredictWidth / 2) { 161 val lastIsValidEnd = if (i == 0) { true.B } else { validEnd(i-1) || !HasCExtension.B } 162 validStart(i) := (lastIsValidEnd || !HasCExtension.B) 163 validEnd(i) := validStart(i) && currentIsRVC(i) || !validStart(i) || !HasCExtension.B 164 165 //prepared for last half match 166 val h_lastIsValidEnd = if (i == 0) { false.B } else { h_validEnd(i-1) || !HasCExtension.B } 167 h_validStart(i) := (h_lastIsValidEnd || !HasCExtension.B) 168 h_validEnd(i) := h_validStart(i) && currentIsRVC(i) || !h_validStart(i) || !HasCExtension.B 169 } 170 171 for (i <- 0 until PredictWidth) { 172 val lastIsValidEnd = if (i == 0) { true.B } else { validEnd_diff(i-1) || !HasCExtension.B } 173 validStart_diff(i) := (lastIsValidEnd || !HasCExtension.B) 174 validEnd_diff(i) := validStart_diff(i) && currentIsRVC(i) || !validStart_diff(i) || !HasCExtension.B 175 176 //prepared for last half match 177 val h_lastIsValidEnd = if (i == 0) { false.B } else { h_validEnd_diff(i-1) || !HasCExtension.B } 178 h_validStart_diff(i) := (h_lastIsValidEnd || !HasCExtension.B) 179 h_validEnd_diff(i) := h_validStart_diff(i) && currentIsRVC(i) || !h_validStart_diff(i) || !HasCExtension.B 180 } 181 182 // assume PredictWidth / 2 is a valid start 183 for (i <- PredictWidth / 2 until PredictWidth) { 184 val lastIsValidEnd = if (i == PredictWidth / 2) { true.B } else { validEnd_half(i-1) || !HasCExtension.B } 185 validStart_half(i) := (lastIsValidEnd || !HasCExtension.B) 186 validEnd_half(i) := validStart_half(i) && currentIsRVC(i) || !validStart_half(i) || !HasCExtension.B 187 188 //prepared for last half match 189 val h_lastIsValidEnd = if (i == PredictWidth / 2) { true.B } else { h_validEnd_half(i-1) || !HasCExtension.B } 190 h_validStart_half(i) := (h_lastIsValidEnd || !HasCExtension.B) 191 h_validEnd_half(i) := h_validStart_half(i) && currentIsRVC(i) || !h_validStart_half(i) || !HasCExtension.B 192 } 193 194 // assume PredictWidth / 2 + 1 is a valid start (and PredictWidth / 2 is last half of RVI) 195 for (i <- PredictWidth / 2 + 1 until PredictWidth) { 196 val lastIsValidEnd = if (i == PredictWidth / 2 + 1) { true.B } else { validEnd_halfPlus1(i-1) || !HasCExtension.B } 197 validStart_halfPlus1(i) := (lastIsValidEnd || !HasCExtension.B) 198 validEnd_halfPlus1(i) := validStart_halfPlus1(i) && currentIsRVC(i) || !validStart_halfPlus1(i) || !HasCExtension.B 199 200 //prepared for last half match 201 val h_lastIsValidEnd = if (i == PredictWidth / 2 + 1) { true.B } else { h_validEnd_halfPlus1(i-1) || !HasCExtension.B } 202 h_validStart_halfPlus1(i) := (h_lastIsValidEnd || !HasCExtension.B) 203 h_validEnd_halfPlus1(i) := h_validStart_halfPlus1(i) && currentIsRVC(i) || !h_validStart_halfPlus1(i) || !HasCExtension.B 204 } 205 validStart_halfPlus1(PredictWidth / 2) := false.B // could be true but when true we select half, not halfPlus1 206 validEnd_halfPlus1(PredictWidth / 2) := true.B 207 208 // assume h_PredictWidth / 2 is an end 209 h_validStart_halfPlus1(PredictWidth / 2) := false.B // could be true but when true we select half, not halfPlus1 210 h_validEnd_halfPlus1(PredictWidth / 2) := true.B 211 212 // if PredictWidth / 2 - 1 is a valid end, PredictWidth / 2 is a valid start 213 for (i <- PredictWidth / 2 until PredictWidth) { 214 validStart(i) := Mux(validEnd(PredictWidth / 2 - 1), validStart_half(i), validStart_halfPlus1(i)) 215 validEnd(i) := Mux(validEnd(PredictWidth / 2 - 1), validEnd_half(i), validEnd_halfPlus1(i)) 216 h_validStart(i) := Mux(h_validEnd(PredictWidth / 2 - 1), h_validStart_half(i), h_validStart_halfPlus1(i)) 217 h_validEnd(i) := Mux(h_validEnd(PredictWidth / 2 - 1), h_validEnd_half(i), h_validEnd_halfPlus1(i)) 218 } 219 220 val validStartMismatch = Wire(Bool()) 221 val validEndMismatch = Wire(Bool()) 222 val validH_ValidStartMismatch = Wire(Bool()) 223 val validH_ValidEndMismatch = Wire(Bool()) 224 225 validStartMismatch := validStart.zip(validStart_diff).map{case(a,b) => a =/= b}.reduce(_||_) 226 validEndMismatch := validEnd.zip(validEnd_diff).map{case(a,b) => a =/= b}.reduce(_||_) 227 validH_ValidStartMismatch := h_validStart.zip(h_validStart_diff).map{case(a,b) => a =/= b}.reduce(_||_) 228 validH_ValidEndMismatch := h_validEnd.zip(h_validEnd_diff).map{case(a,b) => a =/= b}.reduce(_||_) 229 230 XSError(io.in.valid && validStartMismatch, p"validStart mismatch\n") 231 XSError(io.in.valid && validEndMismatch, p"validEnd mismatch\n") 232 XSError(io.in.valid && validH_ValidStartMismatch, p"h_validStart mismatch\n") 233 XSError(io.in.valid && validH_ValidEndMismatch, p"h_validEnd mismatch\n") 234 235// io.out.hasLastHalf := !io.out.pd(PredictWidth - 1).isRVC && io.out.pd(PredictWidth - 1).valid 236 237 for (i <- 0 until PredictWidth) { 238 XSDebug(true.B, 239 p"instr ${Hexadecimal(io.out.instr(i))}, " + 240 p"validStart ${Binary(validStart(i))}, " + 241 p"validEnd ${Binary(validEnd(i))}, " + 242 p"isRVC ${Binary(io.out.pd(i).isRVC)}, " + 243 p"brType ${Binary(io.out.pd(i).brType)}, " + 244 p"isRet ${Binary(io.out.pd(i).isRet)}, " + 245 p"isCall ${Binary(io.out.pd(i).isCall)}\n" 246 ) 247 } 248} 249 250class IfuToF3PreDecode(implicit p: Parameters) extends XSBundle with HasPdConst { 251 val instr = Vec(PredictWidth, UInt(32.W)) 252} 253 254class F3PreDecodeResp(implicit p: Parameters) extends XSBundle with HasPdConst { 255 val pd = Vec(PredictWidth, new PreDecodeInfo) 256} 257class F3Predecoder(implicit p: Parameters) extends XSModule with HasPdConst { 258 val io = IO(new Bundle() { 259 val in = Input(new IfuToF3PreDecode) 260 val out = Output(new F3PreDecodeResp) 261 }) 262 io.out.pd.zipWithIndex.map{ case (pd,i) => 263 pd.valid := DontCare 264 pd.isRVC := DontCare 265 pd.brType := brInfo(io.in.instr(i))(0) 266 pd.isCall := brInfo(io.in.instr(i))(1) 267 pd.isRet := brInfo(io.in.instr(i))(2) 268 } 269 270} 271 272class RVCExpander(implicit p: Parameters) extends XSModule { 273 val io = IO(new Bundle { 274 val in = Input(UInt(32.W)) 275 val out = Output(new ExpandedInstruction) 276 }) 277 278 if (HasCExtension) { 279 io.out := new RVCDecoder(io.in, XLEN, fLen, useAddiForMv = true).decode 280 } else { 281 io.out := new RVCDecoder(io.in, XLEN, fLen, useAddiForMv = true).passthrough 282 } 283} 284 285/* --------------------------------------------------------------------- 286 * Predict result check 287 * 288 * --------------------------------------------------------------------- 289 */ 290 291object FaultType { 292 def noFault = "b000".U 293 def jalFault = "b001".U //not CFI taken or invalid instruction taken 294 def retFault = "b010".U //not CFI taken or invalid instruction taken 295 def targetFault = "b011".U 296 def notCFIFault = "b100".U //not CFI taken or invalid instruction taken 297 def invalidTaken = "b101".U 298 def apply() = UInt(3.W) 299} 300 301class CheckInfo extends Bundle { // 8 bit 302 val value = UInt(3.W) 303 def isjalFault = value === FaultType.jalFault 304 def isRetFault = value === FaultType.retFault 305 def istargetFault = value === FaultType.targetFault 306 def invalidTakenFault = value === FaultType.invalidTaken 307 def notCFIFault = value === FaultType.notCFIFault 308} 309 310class PredCheckerResp(implicit p: Parameters) extends XSBundle with HasPdConst { 311 //to Ibuffer write port (stage 1) 312 val stage1Out = new Bundle{ 313 val fixedRange = Vec(PredictWidth, Bool()) 314 val fixedTaken = Vec(PredictWidth, Bool()) 315 } 316 //to Ftq write back port (stage 2) 317 val stage2Out = new Bundle{ 318 val fixedTarget = Vec(PredictWidth, UInt(VAddrBits.W)) 319 val jalTarget = Vec(PredictWidth, UInt(VAddrBits.W)) 320 val fixedMissPred = Vec(PredictWidth, Bool()) 321 val faultType = Vec(PredictWidth, new CheckInfo) 322 } 323} 324 325 326class PredChecker(implicit p: Parameters) extends XSModule with HasPdConst { 327 val io = IO( new Bundle{ 328 val in = Input(new IfuToPredChecker) 329 val out = Output(new PredCheckerResp) 330 }) 331 332 val (takenIdx, predTaken) = (io.in.ftqOffset.bits, io.in.ftqOffset.valid) 333 val predTarget = (io.in.target) 334 val (instrRange, instrValid) = (io.in.instrRange, io.in.instrValid) 335 val (pds, pc, jumpOffset) = (io.in.pds, io.in.pc, io.in.jumpOffset) 336 337 val jalFaultVec, retFaultVec, targetFault, notCFITaken, invalidTaken = Wire(Vec(PredictWidth, Bool())) 338 339 /** remask fault may appear together with other faults, but other faults are exclusive 340 * so other f ault mast use fixed mask to keep only one fault would be found and redirect to Ftq 341 * we first detecct remask fault and then use fixedRange to do second check 342 **/ 343 344 //Stage 1: detect remask fault 345 /** first check: remask Fault */ 346 jalFaultVec := VecInit(pds.zipWithIndex.map{case(pd, i) => pd.isJal && instrRange(i) && instrValid(i) && (takenIdx > i.U && predTaken || !predTaken) }) 347 retFaultVec := VecInit(pds.zipWithIndex.map{case(pd, i) => pd.isRet && instrRange(i) && instrValid(i) && (takenIdx > i.U && predTaken || !predTaken) }) 348 val remaskFault = VecInit((0 until PredictWidth).map(i => jalFaultVec(i) || retFaultVec(i))) 349 val remaskIdx = ParallelPriorityEncoder(remaskFault.asUInt) 350 val needRemask = ParallelOR(remaskFault) 351 val fixedRange = instrRange.asUInt & (Fill(PredictWidth, !needRemask) | Fill(PredictWidth, 1.U(1.W)) >> ~remaskIdx) 352 353 io.out.stage1Out.fixedRange := fixedRange.asTypeOf((Vec(PredictWidth, Bool()))) 354 355 io.out.stage1Out.fixedTaken := VecInit(pds.zipWithIndex.map{case(pd, i) => instrValid (i) && fixedRange(i) && (pd.isRet || pd.isJal || takenIdx === i.U && predTaken && !pd.notCFI) }) 356 357 /** second check: faulse prediction fault and target fault */ 358 notCFITaken := VecInit(pds.zipWithIndex.map{case(pd, i) => fixedRange(i) && instrValid(i) && i.U === takenIdx && pd.notCFI && predTaken }) 359 invalidTaken := VecInit(pds.zipWithIndex.map{case(pd, i) => fixedRange(i) && !instrValid(i) && i.U === takenIdx && predTaken }) 360 361 val jumpTargets = VecInit(pds.zipWithIndex.map{case(pd,i) => (pc(i) + jumpOffset(i)).asTypeOf(UInt(VAddrBits.W))}) 362 val seqTargets = VecInit((0 until PredictWidth).map(i => pc(i) + Mux(pds(i).isRVC || !instrValid(i), 2.U, 4.U ) )) 363 364 //Stage 2: detect target fault 365 /** target calculation: in the next stage */ 366 val fixedRangeNext = RegEnable(fixedRange, io.in.fire_in) 367 val instrValidNext = RegEnable(instrValid, io.in.fire_in) 368 val takenIdxNext = RegEnable(takenIdx, io.in.fire_in) 369 val predTakenNext = RegEnable(predTaken, io.in.fire_in) 370 val predTargetNext = RegEnable(predTarget, io.in.fire_in) 371 val jumpTargetsNext = RegEnable(jumpTargets, io.in.fire_in) 372 val seqTargetsNext = RegEnable(seqTargets, io.in.fire_in) 373 val pdsNext = RegEnable(pds, io.in.fire_in) 374 val jalFaultVecNext = RegEnable(jalFaultVec, io.in.fire_in) 375 val retFaultVecNext = RegEnable(retFaultVec, io.in.fire_in) 376 val notCFITakenNext = RegEnable(notCFITaken, io.in.fire_in) 377 val invalidTakenNext = RegEnable(invalidTaken, io.in.fire_in) 378 379 targetFault := VecInit(pdsNext.zipWithIndex.map{case(pd,i) => fixedRangeNext(i) && instrValidNext(i) && (pd.isJal || pd.isBr) && takenIdxNext === i.U && predTakenNext && (predTargetNext =/= jumpTargetsNext(i))}) 380 381 382 io.out.stage2Out.faultType.zipWithIndex.foreach{case(faultType, i) => faultType.value := Mux(jalFaultVecNext(i) , FaultType.jalFault , 383 Mux(retFaultVecNext(i), FaultType.retFault , 384 Mux(targetFault(i), FaultType.targetFault , 385 Mux(notCFITakenNext(i) , FaultType.notCFIFault, 386 Mux(invalidTakenNext(i), FaultType.invalidTaken, FaultType.noFault)))))} 387 388 io.out.stage2Out.fixedMissPred.zipWithIndex.foreach{case(missPred, i ) => missPred := jalFaultVecNext(i) || retFaultVecNext(i) || notCFITakenNext(i) || invalidTakenNext(i) || targetFault(i)} 389 io.out.stage2Out.fixedTarget.zipWithIndex.foreach{case(target, i) => target := Mux(jalFaultVecNext(i) || targetFault(i), jumpTargetsNext(i), seqTargetsNext(i) )} 390 io.out.stage2Out.jalTarget.zipWithIndex.foreach{case(target, i) => target := jumpTargetsNext(i) } 391 392} 393 394class FrontendTrigger(implicit p: Parameters) extends XSModule with SdtrigExt { 395 val io = IO(new Bundle(){ 396 val frontendTrigger = Input(new FrontendTdataDistributeIO) 397 val triggered = Output(Vec(PredictWidth, TriggerAction())) 398 399 val pds = Input(Vec(PredictWidth, new PreDecodeInfo)) 400 val pc = Input(Vec(PredictWidth, UInt(VAddrBits.W))) 401 val data = if(HasCExtension) Input(Vec(PredictWidth + 1, UInt(16.W))) 402 else Input(Vec(PredictWidth, UInt(32.W))) 403 }) 404 405 val data = io.data 406 407 val rawInsts = if (HasCExtension) VecInit((0 until PredictWidth).map(i => Cat(data(i+1), data(i)))) 408 else VecInit((0 until PredictWidth).map(i => data(i))) 409 410 val tdataVec = RegInit(VecInit(Seq.fill(TriggerNum)(0.U.asTypeOf(new MatchTriggerIO)))) 411 when(io.frontendTrigger.tUpdate.valid) { 412 tdataVec(io.frontendTrigger.tUpdate.bits.addr) := io.frontendTrigger.tUpdate.bits.tdata 413 } 414 val triggerEnableVec = RegInit(VecInit(Seq.fill(TriggerNum)(false.B))) // From CSR, controlled by priv mode, etc. 415 triggerEnableVec := io.frontendTrigger.tEnableVec 416 XSDebug(triggerEnableVec.asUInt.orR, "Debug Mode: At least one frontend trigger is enabled\n") 417 418 val triggerTimingVec = VecInit(tdataVec.map(_.timing)) 419 val triggerChainVec = VecInit(tdataVec.map(_.chain)) 420 421 for (i <- 0 until TriggerNum) { PrintTriggerInfo(triggerEnableVec(i), tdataVec(i)) } 422 423 val debugMode = io.frontendTrigger.debugMode 424 val triggerCanRaiseBpExp = io.frontendTrigger.triggerCanRaiseBpExp 425 //val triggerHitVec = Wire(Vec(PredictWidth, Vec(TriggerNum, Bool()))) 426 val triggerHitVec = (0 until TriggerNum).map(j => 427 TriggerCmpConsecutive(io.pc, tdataVec(j).tdata2, tdataVec(j).matchType, triggerEnableVec(j)).map( 428 hit => hit && !tdataVec(j).select && !debugMode) 429 ).transpose 430 431 for (i <- 0 until PredictWidth) { 432 val triggerCanFireVec = Wire(Vec(TriggerNum, Bool())) 433 TriggerCheckCanFire(TriggerNum, triggerCanFireVec, VecInit(triggerHitVec(i)), triggerTimingVec, triggerChainVec) 434 435 val actionVec = VecInit(tdataVec.map(_.action)) 436 val triggerAction = Wire(TriggerAction()) 437 TriggerUtil.triggerActionGen(triggerAction, triggerCanFireVec, actionVec, triggerCanRaiseBpExp) 438 439 // Priority may select last when no trigger fire. 440 io.triggered(i) := triggerAction 441 XSDebug(triggerCanFireVec.asUInt.orR, p"Debug Mode: Predecode Inst No. ${i} has trigger action vec ${triggerCanFireVec.asUInt.orR}\n") 442 } 443} 444