1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.frontend 18 19import org.chipsalliance.cde.config.Parameters 20import freechips.rocketchip.rocket.{RVCDecoder, ExpandedInstruction} 21import chisel3.{util, _} 22import chisel3.util._ 23import utils._ 24import utility._ 25import xiangshan._ 26import xiangshan.frontend.icache._ 27import xiangshan.backend.decode.isa.predecode.PreDecodeInst 28import java.lang.reflect.Parameter 29 30trait HasPdConst extends HasXSParameter with HasICacheParameters with HasIFUConst{ 31 def isRVC(inst: UInt) = (inst(1,0) =/= 3.U) 32 def isLink(reg:UInt) = reg === 1.U || reg === 5.U 33 def brInfo(instr: UInt) = { 34 val brType::Nil = ListLookup(instr, List(BrType.notCFI), PreDecodeInst.brTable) 35 val rd = Mux(isRVC(instr), instr(12), instr(11,7)) 36 val rs = Mux(isRVC(instr), Mux(brType === BrType.jal, 0.U, instr(11, 7)), instr(19, 15)) 37 val isCall = (brType === BrType.jal && !isRVC(instr) || brType === BrType.jalr) && isLink(rd) // Only for RV64 38 val isRet = brType === BrType.jalr && isLink(rs) && !isCall 39 List(brType, isCall, isRet) 40 } 41 def jal_offset(inst: UInt, rvc: Bool): UInt = { 42 val rvc_offset = Cat(inst(12), inst(8), inst(10, 9), inst(6), inst(7), inst(2), inst(11), inst(5, 3), 0.U(1.W)) 43 val rvi_offset = Cat(inst(31), inst(19, 12), inst(20), inst(30, 21), 0.U(1.W)) 44 val max_width = rvi_offset.getWidth 45 SignExt(Mux(rvc, SignExt(rvc_offset, max_width), SignExt(rvi_offset, max_width)), XLEN) 46 } 47 def br_offset(inst: UInt, rvc: Bool): UInt = { 48 val rvc_offset = Cat(inst(12), inst(6, 5), inst(2), inst(11, 10), inst(4, 3), 0.U(1.W)) 49 val rvi_offset = Cat(inst(31), inst(7), inst(30, 25), inst(11, 8), 0.U(1.W)) 50 val max_width = rvi_offset.getWidth 51 SignExt(Mux(rvc, SignExt(rvc_offset, max_width), SignExt(rvi_offset, max_width)), XLEN) 52 } 53 54 def NOP = "h4501".U(16.W) 55} 56 57object BrType { 58 def notCFI = "b00".U 59 def branch = "b01".U 60 def jal = "b10".U 61 def jalr = "b11".U 62 def apply() = UInt(2.W) 63} 64 65object ExcType { //TODO:add exctype 66 def notExc = "b000".U 67 def apply() = UInt(3.W) 68} 69 70class PreDecodeInfo extends Bundle { // 8 bit 71 val valid = Bool() 72 val isRVC = Bool() 73 val brType = UInt(2.W) 74 val isCall = Bool() 75 val isRet = Bool() 76 //val excType = UInt(3.W) 77 def isBr = brType === BrType.branch 78 def isJal = brType === BrType.jal 79 def isJalr = brType === BrType.jalr 80 def notCFI = brType === BrType.notCFI 81} 82 83class PreDecodeResp(implicit p: Parameters) extends XSBundle with HasPdConst { 84 val pd = Vec(PredictWidth, new PreDecodeInfo) 85 val hasHalfValid = Vec(PredictWidth, Bool()) 86 //val expInstr = Vec(PredictWidth, UInt(32.W)) 87 val instr = Vec(PredictWidth, UInt(32.W)) 88 val jumpOffset = Vec(PredictWidth, UInt(XLEN.W)) 89// val hasLastHalf = Bool() 90 val triggered = Vec(PredictWidth, new TriggerCf) 91} 92 93class PreDecode(implicit p: Parameters) extends XSModule with HasPdConst{ 94 val io = IO(new Bundle() { 95 val in = Input(new IfuToPreDecode) 96 val out = Output(new PreDecodeResp) 97 }) 98 99 val data = io.in.data 100// val lastHalfMatch = io.in.lastHalfMatch 101 val validStart, validEnd = Wire(Vec(PredictWidth, Bool())) 102 val h_validStart, h_validEnd = Wire(Vec(PredictWidth, Bool())) 103 104 val validStart_half, validEnd_half = Wire(Vec(PredictWidth, Bool())) 105 val h_validStart_half, h_validEnd_half = Wire(Vec(PredictWidth, Bool())) 106 107 val validStart_halfPlus1, validEnd_halfPlus1 = Wire(Vec(PredictWidth, Bool())) 108 val h_validStart_halfPlus1, h_validEnd_halfPlus1 = Wire(Vec(PredictWidth, Bool())) 109 110 val validStart_diff, validEnd_diff = Wire(Vec(PredictWidth, Bool())) 111 val h_validStart_diff, h_validEnd_diff = Wire(Vec(PredictWidth, Bool())) 112 113 val currentIsRVC = Wire(Vec(PredictWidth, Bool())) 114 115 validStart_half.map(_ := false.B) 116 validEnd_half.map(_ := false.B) 117 h_validStart_half.map(_ := false.B) 118 h_validEnd_half.map(_ := false.B) 119 120 validStart_halfPlus1.map(_ := false.B) 121 validEnd_halfPlus1.map(_ := false.B) 122 h_validStart_halfPlus1.map(_ := false.B) 123 h_validEnd_halfPlus1.map(_ := false.B) 124 125 dontTouch(validStart_half) 126 dontTouch(validEnd_half) 127 dontTouch(h_validStart_half) 128 dontTouch(h_validEnd_half) 129 dontTouch(validStart_halfPlus1) 130 dontTouch(validEnd_halfPlus1) 131 dontTouch(h_validStart_halfPlus1) 132 dontTouch(h_validEnd_halfPlus1) 133 dontTouch(validStart_diff) 134 dontTouch(validEnd_diff) 135 dontTouch(h_validStart_diff) 136 dontTouch(h_validEnd_diff) 137 dontTouch(validStart) 138 dontTouch(validEnd) 139 dontTouch(h_validStart) 140 dontTouch(h_validEnd) 141 142 val rawInsts = if (HasCExtension) VecInit((0 until PredictWidth).map(i => Cat(data(i+1), data(i)))) 143 else VecInit((0 until PredictWidth).map(i => data(i))) 144 145 for (i <- 0 until PredictWidth) { 146 val inst = WireInit(rawInsts(i)) 147 //val expander = Module(new RVCExpander) 148 currentIsRVC(i) := isRVC(inst) 149 val currentPC = io.in.pc(i) 150 //expander.io.in := inst 151 152 val brType::isCall::isRet::Nil = brInfo(inst) 153 val jalOffset = jal_offset(inst, currentIsRVC(i)) 154 val brOffset = br_offset(inst, currentIsRVC(i)) 155 156 io.out.hasHalfValid(i) := h_validStart(i) 157 158 io.out.triggered(i) := DontCare//VecInit(Seq.fill(10)(false.B)) 159 160 161 io.out.pd(i).valid := validStart(i) 162 io.out.pd(i).isRVC := currentIsRVC(i) 163 164 // for diff purpose only 165 io.out.pd(i).brType := brType 166 io.out.pd(i).isCall := isCall 167 io.out.pd(i).isRet := isRet 168 169 //io.out.expInstr(i) := expander.io.out.bits 170 io.out.instr(i) :=inst 171 io.out.jumpOffset(i) := Mux(io.out.pd(i).isBr, brOffset, jalOffset) 172 } 173 174 // the first half is always reliable 175 for (i <- 0 until PredictWidth / 2) { 176 val lastIsValidEnd = if (i == 0) { true.B } else { validEnd(i-1) || !HasCExtension.B } 177 validStart(i) := (lastIsValidEnd || !HasCExtension.B) 178 validEnd(i) := validStart(i) && currentIsRVC(i) || !validStart(i) || !HasCExtension.B 179 180 //prepared for last half match 181 val h_lastIsValidEnd = if (i == 0) { false.B } else { h_validEnd(i-1) || !HasCExtension.B } 182 h_validStart(i) := (h_lastIsValidEnd || !HasCExtension.B) 183 h_validEnd(i) := h_validStart(i) && currentIsRVC(i) || !h_validStart(i) || !HasCExtension.B 184 } 185 186 for (i <- 0 until PredictWidth) { 187 val lastIsValidEnd = if (i == 0) { true.B } else { validEnd_diff(i-1) || !HasCExtension.B } 188 validStart_diff(i) := (lastIsValidEnd || !HasCExtension.B) 189 validEnd_diff(i) := validStart_diff(i) && currentIsRVC(i) || !validStart_diff(i) || !HasCExtension.B 190 191 //prepared for last half match 192 val h_lastIsValidEnd = if (i == 0) { false.B } else { h_validEnd_diff(i-1) || !HasCExtension.B } 193 h_validStart_diff(i) := (h_lastIsValidEnd || !HasCExtension.B) 194 h_validEnd_diff(i) := h_validStart_diff(i) && currentIsRVC(i) || !h_validStart_diff(i) || !HasCExtension.B 195 } 196 197 // assume PredictWidth / 2 is a valid start 198 for (i <- PredictWidth / 2 until PredictWidth) { 199 val lastIsValidEnd = if (i == PredictWidth / 2) { true.B } else { validEnd_half(i-1) || !HasCExtension.B } 200 validStart_half(i) := (lastIsValidEnd || !HasCExtension.B) 201 validEnd_half(i) := validStart_half(i) && currentIsRVC(i) || !validStart_half(i) || !HasCExtension.B 202 203 //prepared for last half match 204 val h_lastIsValidEnd = if (i == PredictWidth / 2) { true.B } else { h_validEnd_half(i-1) || !HasCExtension.B } 205 h_validStart_half(i) := (h_lastIsValidEnd || !HasCExtension.B) 206 h_validEnd_half(i) := h_validStart_half(i) && currentIsRVC(i) || !h_validStart_half(i) || !HasCExtension.B 207 } 208 209 // assume PredictWidth / 2 + 1 is a valid start (and PredictWidth / 2 is last half of RVI) 210 for (i <- PredictWidth / 2 + 1 until PredictWidth) { 211 val lastIsValidEnd = if (i == PredictWidth / 2 + 1) { true.B } else { validEnd_halfPlus1(i-1) || !HasCExtension.B } 212 validStart_halfPlus1(i) := (lastIsValidEnd || !HasCExtension.B) 213 validEnd_halfPlus1(i) := validStart_halfPlus1(i) && currentIsRVC(i) || !validStart_halfPlus1(i) || !HasCExtension.B 214 215 //prepared for last half match 216 val h_lastIsValidEnd = if (i == PredictWidth / 2 + 1) { true.B } else { h_validEnd_halfPlus1(i-1) || !HasCExtension.B } 217 h_validStart_halfPlus1(i) := (h_lastIsValidEnd || !HasCExtension.B) 218 h_validEnd_halfPlus1(i) := h_validStart_halfPlus1(i) && currentIsRVC(i) || !h_validStart_halfPlus1(i) || !HasCExtension.B 219 } 220 validStart_halfPlus1(PredictWidth / 2) := false.B // could be true but when true we select half, not halfPlus1 221 validEnd_halfPlus1(PredictWidth / 2) := true.B 222 223 // assume h_PredictWidth / 2 is an end 224 h_validStart_halfPlus1(PredictWidth / 2) := false.B // could be true but when true we select half, not halfPlus1 225 h_validEnd_halfPlus1(PredictWidth / 2) := true.B 226 227 // if PredictWidth / 2 - 1 is a valid end, PredictWidth / 2 is a valid start 228 for (i <- PredictWidth / 2 until PredictWidth) { 229 validStart(i) := Mux(validEnd(PredictWidth / 2 - 1), validStart_half(i), validStart_halfPlus1(i)) 230 validEnd(i) := Mux(validEnd(PredictWidth / 2 - 1), validEnd_half(i), validEnd_halfPlus1(i)) 231 h_validStart(i) := Mux(h_validEnd(PredictWidth / 2 - 1), h_validStart_half(i), h_validStart_halfPlus1(i)) 232 h_validEnd(i) := Mux(h_validEnd(PredictWidth / 2 - 1), h_validEnd_half(i), h_validEnd_halfPlus1(i)) 233 } 234 235 val validStartMismatch = Wire(Bool()) 236 val validEndMismatch = Wire(Bool()) 237 val validH_ValidStartMismatch = Wire(Bool()) 238 val validH_ValidEndMismatch = Wire(Bool()) 239 240 validStartMismatch := validStart.zip(validStart_diff).map{case(a,b) => a =/= b}.reduce(_||_) 241 validEndMismatch := validEnd.zip(validEnd_diff).map{case(a,b) => a =/= b}.reduce(_||_) 242 validH_ValidStartMismatch := h_validStart.zip(h_validStart_diff).map{case(a,b) => a =/= b}.reduce(_||_) 243 validH_ValidEndMismatch := h_validEnd.zip(h_validEnd_diff).map{case(a,b) => a =/= b}.reduce(_||_) 244 245 XSError(validStartMismatch, p"validStart mismatch\n") 246 XSError(validEndMismatch, p"validEnd mismatch\n") 247 XSError(validH_ValidStartMismatch, p"h_validStart mismatch\n") 248 XSError(validH_ValidEndMismatch, p"h_validEnd mismatch\n") 249 250// io.out.hasLastHalf := !io.out.pd(PredictWidth - 1).isRVC && io.out.pd(PredictWidth - 1).valid 251 252 for (i <- 0 until PredictWidth) { 253 XSDebug(true.B, 254 p"instr ${Hexadecimal(io.out.instr(i))}, " + 255 p"validStart ${Binary(validStart(i))}, " + 256 p"validEnd ${Binary(validEnd(i))}, " + 257 p"isRVC ${Binary(io.out.pd(i).isRVC)}, " + 258 p"brType ${Binary(io.out.pd(i).brType)}, " + 259 p"isRet ${Binary(io.out.pd(i).isRet)}, " + 260 p"isCall ${Binary(io.out.pd(i).isCall)}\n" 261 ) 262 } 263} 264 265class IfuToF3PreDecode(implicit p: Parameters) extends XSBundle with HasPdConst { 266 val instr = Vec(PredictWidth, UInt(32.W)) 267} 268 269class F3PreDecodeResp(implicit p: Parameters) extends XSBundle with HasPdConst { 270 val pd = Vec(PredictWidth, new PreDecodeInfo) 271} 272class F3Predecoder(implicit p: Parameters) extends XSModule with HasPdConst { 273 val io = IO(new Bundle() { 274 val in = Input(new IfuToF3PreDecode) 275 val out = Output(new F3PreDecodeResp) 276 }) 277 io.out.pd.zipWithIndex.map{ case (pd,i) => 278 pd.valid := DontCare 279 pd.isRVC := DontCare 280 pd.brType := brInfo(io.in.instr(i))(0) 281 pd.isCall := brInfo(io.in.instr(i))(1) 282 pd.isRet := brInfo(io.in.instr(i))(2) 283 } 284 285} 286 287class RVCExpander(implicit p: Parameters) extends XSModule { 288 val io = IO(new Bundle { 289 val in = Input(UInt(32.W)) 290 val out = Output(new ExpandedInstruction) 291 }) 292 293 if (HasCExtension) { 294 io.out := new RVCDecoder(io.in, XLEN, useAddiForMv = true).decode 295 } else { 296 io.out := new RVCDecoder(io.in, XLEN, useAddiForMv = true).passthrough 297 } 298} 299 300/* --------------------------------------------------------------------- 301 * Predict result check 302 * 303 * --------------------------------------------------------------------- 304 */ 305 306object FaultType { 307 def noFault = "b000".U 308 def jalFault = "b001".U //not CFI taken or invalid instruction taken 309 def retFault = "b010".U //not CFI taken or invalid instruction taken 310 def targetFault = "b011".U 311 def notCFIFault = "b100".U //not CFI taken or invalid instruction taken 312 def invalidTaken = "b101".U 313 def apply() = UInt(3.W) 314} 315 316class CheckInfo extends Bundle { // 8 bit 317 val value = UInt(3.W) 318 def isjalFault = value === FaultType.jalFault 319 def isRetFault = value === FaultType.retFault 320 def istargetFault = value === FaultType.targetFault 321 def invalidTakenFault = value === FaultType.invalidTaken 322 def notCFIFault = value === FaultType.notCFIFault 323} 324 325class PredCheckerResp(implicit p: Parameters) extends XSBundle with HasPdConst { 326 //to Ibuffer write port (stage 1) 327 val stage1Out = new Bundle{ 328 val fixedRange = Vec(PredictWidth, Bool()) 329 val fixedTaken = Vec(PredictWidth, Bool()) 330 } 331 //to Ftq write back port (stage 2) 332 val stage2Out = new Bundle{ 333 val fixedTarget = Vec(PredictWidth, UInt(VAddrBits.W)) 334 val jalTarget = Vec(PredictWidth, UInt(VAddrBits.W)) 335 val fixedMissPred = Vec(PredictWidth, Bool()) 336 val faultType = Vec(PredictWidth, new CheckInfo) 337 } 338} 339 340 341class PredChecker(implicit p: Parameters) extends XSModule with HasPdConst { 342 val io = IO( new Bundle{ 343 val in = Input(new IfuToPredChecker) 344 val out = Output(new PredCheckerResp) 345 }) 346 347 val (takenIdx, predTaken) = (io.in.ftqOffset.bits, io.in.ftqOffset.valid) 348 val predTarget = (io.in.target) 349 val (instrRange, instrValid) = (io.in.instrRange, io.in.instrValid) 350 val (pds, pc, jumpOffset) = (io.in.pds, io.in.pc, io.in.jumpOffset) 351 352 val jalFaultVec, retFaultVec, targetFault, notCFITaken, invalidTaken = Wire(Vec(PredictWidth, Bool())) 353 354 /** remask fault may appear together with other faults, but other faults are exclusive 355 * so other f ault mast use fixed mask to keep only one fault would be found and redirect to Ftq 356 * we first detecct remask fault and then use fixedRange to do second check 357 **/ 358 359 //Stage 1: detect remask fault 360 /** first check: remask Fault */ 361 jalFaultVec := VecInit(pds.zipWithIndex.map{case(pd, i) => pd.isJal && instrRange(i) && instrValid(i) && (takenIdx > i.U && predTaken || !predTaken) }) 362 retFaultVec := VecInit(pds.zipWithIndex.map{case(pd, i) => pd.isRet && instrRange(i) && instrValid(i) && (takenIdx > i.U && predTaken || !predTaken) }) 363 val remaskFault = VecInit((0 until PredictWidth).map(i => jalFaultVec(i) || retFaultVec(i))) 364 val remaskIdx = ParallelPriorityEncoder(remaskFault.asUInt) 365 val needRemask = ParallelOR(remaskFault) 366 val fixedRange = instrRange.asUInt & (Fill(PredictWidth, !needRemask) | Fill(PredictWidth, 1.U(1.W)) >> ~remaskIdx) 367 368 io.out.stage1Out.fixedRange := fixedRange.asTypeOf((Vec(PredictWidth, Bool()))) 369 370 io.out.stage1Out.fixedTaken := VecInit(pds.zipWithIndex.map{case(pd, i) => instrValid (i) && fixedRange(i) && (pd.isRet || pd.isJal || takenIdx === i.U && predTaken && !pd.notCFI) }) 371 372 /** second check: faulse prediction fault and target fault */ 373 notCFITaken := VecInit(pds.zipWithIndex.map{case(pd, i) => fixedRange(i) && instrValid(i) && i.U === takenIdx && pd.notCFI && predTaken }) 374 invalidTaken := VecInit(pds.zipWithIndex.map{case(pd, i) => fixedRange(i) && !instrValid(i) && i.U === takenIdx && predTaken }) 375 376 val jumpTargets = VecInit(pds.zipWithIndex.map{case(pd,i) => (pc(i) + jumpOffset(i)).asTypeOf(UInt(VAddrBits.W))}) 377 val seqTargets = VecInit((0 until PredictWidth).map(i => pc(i) + Mux(pds(i).isRVC || !instrValid(i), 2.U, 4.U ) )) 378 379 //Stage 2: detect target fault 380 /** target calculation: in the next stage */ 381 val fixedRangeNext = RegNext(fixedRange) 382 val instrValidNext = RegNext(instrValid) 383 val takenIdxNext = RegNext(takenIdx) 384 val predTakenNext = RegNext(predTaken) 385 val predTargetNext = RegNext(predTarget) 386 val jumpTargetsNext = RegNext(jumpTargets) 387 val seqTargetsNext = RegNext(seqTargets) 388 val pdsNext = RegNext(pds) 389 val jalFaultVecNext = RegNext(jalFaultVec) 390 val retFaultVecNext = RegNext(retFaultVec) 391 val notCFITakenNext = RegNext(notCFITaken) 392 val invalidTakenNext = RegNext(invalidTaken) 393 394 targetFault := VecInit(pdsNext.zipWithIndex.map{case(pd,i) => fixedRangeNext(i) && instrValidNext(i) && (pd.isJal || pd.isBr) && takenIdxNext === i.U && predTakenNext && (predTargetNext =/= jumpTargetsNext(i))}) 395 396 397 io.out.stage2Out.faultType.zipWithIndex.map{case(faultType, i) => faultType.value := Mux(jalFaultVecNext(i) , FaultType.jalFault , 398 Mux(retFaultVecNext(i), FaultType.retFault , 399 Mux(targetFault(i), FaultType.targetFault , 400 Mux(notCFITakenNext(i) , FaultType.notCFIFault, 401 Mux(invalidTakenNext(i), FaultType.invalidTaken, FaultType.noFault)))))} 402 403 io.out.stage2Out.fixedMissPred.zipWithIndex.map{case(missPred, i ) => missPred := jalFaultVecNext(i) || retFaultVecNext(i) || notCFITakenNext(i) || invalidTakenNext(i) || targetFault(i)} 404 io.out.stage2Out.fixedTarget.zipWithIndex.map{case(target, i) => target := Mux(jalFaultVecNext(i) || targetFault(i), jumpTargetsNext(i), seqTargetsNext(i) )} 405 io.out.stage2Out.jalTarget.zipWithIndex.map{case(target, i) => target := jumpTargetsNext(i) } 406 407} 408 409class FrontendTrigger(implicit p: Parameters) extends XSModule { 410 val io = IO(new Bundle(){ 411 val frontendTrigger = Input(new FrontendTdataDistributeIO) 412 val csrTriggerEnable = Input(Vec(4, Bool())) 413 val triggered = Output(Vec(PredictWidth, new TriggerCf)) 414 415 val pds = Input(Vec(PredictWidth, new PreDecodeInfo)) 416 val pc = Input(Vec(PredictWidth, UInt(VAddrBits.W))) 417 val data = if(HasCExtension) Input(Vec(PredictWidth + 1, UInt(16.W))) 418 else Input(Vec(PredictWidth, UInt(32.W))) 419 }) 420 421 val data = io.data 422 423 val rawInsts = if (HasCExtension) VecInit((0 until PredictWidth).map(i => Cat(data(i+1), data(i)))) 424 else VecInit((0 until PredictWidth).map(i => data(i))) 425 426 val tdata = RegInit(VecInit(Seq.fill(4)(0.U.asTypeOf(new MatchTriggerIO)))) 427 when(io.frontendTrigger.t.valid) { 428 tdata(io.frontendTrigger.t.bits.addr) := io.frontendTrigger.t.bits.tdata 429 } 430 io.triggered.map{i => i := 0.U.asTypeOf(new TriggerCf)} 431 val triggerEnable = RegInit(VecInit(Seq.fill(4)(false.B))) // From CSR, controlled by priv mode, etc. 432 triggerEnable := io.csrTriggerEnable 433 XSDebug(triggerEnable.asUInt.orR, "Debug Mode: At least one frontend trigger is enabled\n") 434 435 for (i <- 0 until 4) {PrintTriggerInfo(triggerEnable(i), tdata(i))} 436 437 for (i <- 0 until PredictWidth) { 438 val currentPC = io.pc(i) 439 val currentIsRVC = io.pds(i).isRVC 440 val inst = WireInit(rawInsts(i)) 441 val triggerHitVec = Wire(Vec(4, Bool())) 442 443 for (j <- 0 until 4) { 444 triggerHitVec(j) := Mux(tdata(j).select, TriggerCmp(Mux(currentIsRVC, inst(15, 0), inst), tdata(j).tdata2, tdata(j).matchType, triggerEnable(j)), 445 TriggerCmp(currentPC, tdata(j).tdata2, tdata(j).matchType, triggerEnable(j))) 446 } 447 448 // fix chains this could be moved further into the pipeline 449 io.triggered(i).frontendHit := triggerHitVec 450 val enableChain = tdata(0).chain 451 when(enableChain){ 452 io.triggered(i).frontendHit(0) := triggerHitVec(0) && triggerHitVec(1) && (tdata(0).timing === tdata(1).timing) 453 io.triggered(i).frontendHit(1) := triggerHitVec(0) && triggerHitVec(1) && (tdata(0).timing === tdata(1).timing) 454 } 455 for(j <- 0 until 2) { 456 io.triggered(i).backendEn(j) := Mux(tdata(j+2).chain, triggerHitVec(j+2), true.B) 457 io.triggered(i).frontendHit(j+2) := !tdata(j+2).chain && triggerHitVec(j+2) // temporary workaround 458 } 459 XSDebug(io.triggered(i).getHitFrontend, p"Debug Mode: Predecode Inst No. ${i} has trigger hit vec ${io.triggered(i).frontendHit}" + 460 p"and backend en ${io.triggered(i).backendEn}\n") 461 } 462} 463