1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* 4* XiangShan is licensed under Mulan PSL v2. 5* You can use this software according to the terms and conditions of the Mulan PSL v2. 6* You may obtain a copy of Mulan PSL v2 at: 7* http://license.coscl.org.cn/MulanPSL2 8* 9* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 10* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 11* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 12* 13* See the Mulan PSL v2 for more details. 14***************************************************************************************/ 15 16package xiangshan.mem 17 18import chipsalliance.rocketchip.config.Parameters 19import chisel3._ 20import chisel3.util._ 21import utils._ 22import xiangshan._ 23import xiangshan.backend.decode.ImmUnion 24import xiangshan.cache._ 25 26// Store Pipeline Stage 0 27// Generate addr, use addr to query DCache and DTLB 28class StoreUnit_S0(implicit p: Parameters) extends XSModule { 29 val io = IO(new Bundle() { 30 val in = Flipped(Decoupled(new ExuInput)) 31 val rsIdx = Input(UInt(log2Up(IssQueSize).W)) 32 val isFirstIssue = Input(Bool()) 33 val out = Decoupled(new LsPipelineBundle) 34 val dtlbReq = DecoupledIO(new TlbReq) 35 }) 36 37 // send req to dtlb 38 // val saddr = io.in.bits.src(0) + SignExt(io.in.bits.uop.ctrl.imm(11,0), VAddrBits) 39 val imm12 = WireInit(io.in.bits.uop.ctrl.imm(11,0)) 40 val saddr_lo = io.in.bits.src(0)(11,0) + Cat(0.U(1.W), imm12) 41 val saddr_hi = Mux(saddr_lo(12), 42 Mux(imm12(11), io.in.bits.src(0)(VAddrBits-1, 12), io.in.bits.src(0)(VAddrBits-1, 12)+1.U), 43 Mux(imm12(11), io.in.bits.src(0)(VAddrBits-1, 12)+SignExt(1.U, VAddrBits-12), io.in.bits.src(0)(VAddrBits-1, 12)), 44 ) 45 val saddr = Cat(saddr_hi, saddr_lo(11,0)) 46 47 io.dtlbReq.bits.vaddr := saddr 48 io.dtlbReq.valid := io.in.valid 49 io.dtlbReq.bits.cmd := TlbCmd.write 50 io.dtlbReq.bits.roqIdx := io.in.bits.uop.roqIdx 51 io.dtlbReq.bits.debug.pc := io.in.bits.uop.cf.pc 52 io.dtlbReq.bits.debug.isFirstIssue := io.isFirstIssue 53 54 io.out.bits := DontCare 55 io.out.bits.vaddr := saddr 56 57 // Now data use its own io 58 // io.out.bits.data := genWdata(io.in.bits.src(1), io.in.bits.uop.ctrl.fuOpType(1,0)) 59 io.out.bits.data := io.in.bits.src(1) // FIXME: remove data from pipeline 60 io.out.bits.uop := io.in.bits.uop 61 io.out.bits.miss := DontCare 62 io.out.bits.rsIdx := io.rsIdx 63 io.out.bits.mask := genWmask(io.out.bits.vaddr, io.in.bits.uop.ctrl.fuOpType(1,0)) 64 io.out.valid := io.in.valid 65 io.in.ready := io.out.ready 66 67 // exception check 68 val addrAligned = LookupTree(io.in.bits.uop.ctrl.fuOpType(1,0), List( 69 "b00".U -> true.B, //b 70 "b01".U -> (io.out.bits.vaddr(0) === 0.U), //h 71 "b10".U -> (io.out.bits.vaddr(1,0) === 0.U), //w 72 "b11".U -> (io.out.bits.vaddr(2,0) === 0.U) //d 73 )) 74 io.out.bits.uop.cf.exceptionVec(storeAddrMisaligned) := !addrAligned 75 76 XSPerfAccumulate("addr_spec_success", io.out.fire() && saddr(VAddrBits-1, 12) === io.in.bits.src(0)(VAddrBits-1, 12)) 77 XSPerfAccumulate("addr_spec_failed", io.out.fire() && saddr(VAddrBits-1, 12) =/= io.in.bits.src(0)(VAddrBits-1, 12)) 78 XSPerfAccumulate("addr_spec_success_once", io.out.fire() && saddr(VAddrBits-1, 12) === io.in.bits.src(0)(VAddrBits-1, 12) && io.isFirstIssue) 79 XSPerfAccumulate("addr_spec_failed_once", io.out.fire() && saddr(VAddrBits-1, 12) =/= io.in.bits.src(0)(VAddrBits-1, 12) && io.isFirstIssue) 80} 81 82// Load Pipeline Stage 1 83// TLB resp (send paddr to dcache) 84class StoreUnit_S1(implicit p: Parameters) extends XSModule { 85 val io = IO(new Bundle() { 86 val in = Flipped(Decoupled(new LsPipelineBundle)) 87 val out = Decoupled(new LsPipelineBundle) 88 val lsq = ValidIO(new LsPipelineBundle) 89 val dtlbResp = Flipped(DecoupledIO(new TlbResp)) 90 val rsFeedback = ValidIO(new RSFeedback) 91 }) 92 93 val s1_paddr = io.dtlbResp.bits.paddr 94 val s1_tlb_miss = io.dtlbResp.bits.miss 95 val s1_mmio = io.dtlbResp.bits.mmio 96 val s1_exception = selectStore(io.out.bits.uop.cf.exceptionVec, false).asUInt.orR 97 98 io.in.ready := true.B 99 100 io.dtlbResp.ready := true.B // TODO: why dtlbResp needs a ready? 101 102 // Send TLB feedback to store issue queue 103 io.rsFeedback.valid := io.in.valid 104 io.rsFeedback.bits.hit := !s1_tlb_miss 105 io.rsFeedback.bits.flushState := io.dtlbResp.bits.ptwBack 106 io.rsFeedback.bits.rsIdx := io.in.bits.rsIdx 107 io.rsFeedback.bits.sourceType := RSFeedbackType.tlbMiss 108 XSDebug(io.rsFeedback.valid, 109 "S1 Store: tlbHit: %d roqIdx: %d\n", 110 io.rsFeedback.bits.hit, 111 io.rsFeedback.bits.rsIdx 112 ) 113 114 115 // get paddr from dtlb, check if rollback is needed 116 // writeback store inst to lsq 117 io.lsq.valid := io.in.valid && !s1_tlb_miss 118 io.lsq.bits := io.in.bits 119 io.lsq.bits.paddr := s1_paddr 120 io.lsq.bits.miss := false.B 121 io.lsq.bits.mmio := s1_mmio && !s1_exception 122 io.lsq.bits.uop.cf.exceptionVec(storePageFault) := io.dtlbResp.bits.excp.pf.st 123 io.lsq.bits.uop.cf.exceptionVec(storeAccessFault) := io.dtlbResp.bits.excp.af.st 124 125 // mmio inst with exception will be writebacked immediately 126 io.out.valid := io.in.valid && (!io.out.bits.mmio || s1_exception) && !s1_tlb_miss 127 io.out.bits := io.lsq.bits 128} 129 130class StoreUnit_S2(implicit p: Parameters) extends XSModule { 131 val io = IO(new Bundle() { 132 val in = Flipped(Decoupled(new LsPipelineBundle)) 133 val out = Decoupled(new LsPipelineBundle) 134 }) 135 136 io.in.ready := true.B 137 io.out.bits := io.in.bits 138 io.out.valid := io.in.valid 139 140} 141 142class StoreUnit_S3(implicit p: Parameters) extends XSModule { 143 val io = IO(new Bundle() { 144 val in = Flipped(Decoupled(new LsPipelineBundle)) 145 val stout = DecoupledIO(new ExuOutput) // writeback store 146 }) 147 148 io.in.ready := true.B 149 150 io.stout.valid := io.in.valid 151 io.stout.bits.uop := io.in.bits.uop 152 io.stout.bits.data := DontCare 153 io.stout.bits.redirectValid := false.B 154 io.stout.bits.redirect := DontCare 155 io.stout.bits.debug.isMMIO := io.in.bits.mmio 156 io.stout.bits.debug.paddr := DontCare 157 io.stout.bits.debug.isPerfCnt := false.B 158 io.stout.bits.fflags := DontCare 159 160} 161 162class StoreUnit(implicit p: Parameters) extends XSModule { 163 val io = IO(new Bundle() { 164 val stin = Flipped(Decoupled(new ExuInput)) 165 val redirect = Flipped(ValidIO(new Redirect)) 166 val flush = Input(Bool()) 167 val rsFeedback = ValidIO(new RSFeedback) 168 val dtlb = new TlbRequestIO() 169 val rsIdx = Input(UInt(log2Up(IssQueSize).W)) 170 val isFirstIssue = Input(Bool()) 171 val lsq = ValidIO(new LsPipelineBundle) 172 val stout = DecoupledIO(new ExuOutput) // writeback store 173 }) 174 175 val store_s0 = Module(new StoreUnit_S0) 176 val store_s1 = Module(new StoreUnit_S1) 177 val store_s2 = Module(new StoreUnit_S2) 178 val store_s3 = Module(new StoreUnit_S3) 179 180 store_s0.io.in <> io.stin 181 store_s0.io.dtlbReq <> io.dtlb.req 182 store_s0.io.rsIdx := io.rsIdx 183 store_s0.io.isFirstIssue := io.isFirstIssue 184 185 PipelineConnect(store_s0.io.out, store_s1.io.in, true.B, store_s0.io.out.bits.uop.roqIdx.needFlush(io.redirect, io.flush)) 186 187 store_s1.io.lsq <> io.lsq // send result to sq 188 store_s1.io.dtlbResp <> io.dtlb.resp 189 store_s1.io.rsFeedback <> io.rsFeedback 190 191 PipelineConnect(store_s1.io.out, store_s2.io.in, true.B, store_s1.io.out.bits.uop.roqIdx.needFlush(io.redirect, io.flush)) 192 193 PipelineConnect(store_s2.io.out, store_s3.io.in, true.B, store_s2.io.out.bits.uop.roqIdx.needFlush(io.redirect, io.flush)) 194 195 store_s3.io.stout <> io.stout 196 197 private def printPipeLine(pipeline: LsPipelineBundle, cond: Bool, name: String): Unit = { 198 XSDebug(cond, 199 p"$name" + p" pc ${Hexadecimal(pipeline.uop.cf.pc)} " + 200 p"addr ${Hexadecimal(pipeline.vaddr)} -> ${Hexadecimal(pipeline.paddr)} " + 201 p"op ${Binary(pipeline.uop.ctrl.fuOpType)} " + 202 p"data ${Hexadecimal(pipeline.data)} " + 203 p"mask ${Hexadecimal(pipeline.mask)}\n" 204 ) 205 } 206 207 printPipeLine(store_s0.io.out.bits, store_s0.io.out.valid, "S0") 208 printPipeLine(store_s1.io.out.bits, store_s1.io.out.valid, "S1") 209 210} 211