1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.frontend 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import freechips.rocketchip.rocket.{RVCDecoder, ExpandedInstruction} 24import xiangshan._ 25import xiangshan.backend.decode.isa.predecode.PreDecodeInst 26import xiangshan.cache._ 27 28trait HasPdconst{ this: XSModule => 29 def isRVC(inst: UInt) = (inst(1,0) =/= 3.U) 30 def isLink(reg:UInt) = reg === 1.U || reg === 5.U 31 def brInfo(instr: UInt) = { 32 val brType::Nil = ListLookup(instr, List(BrType.notBr), PreDecodeInst.brTable) 33 val rd = Mux(isRVC(instr), instr(12), instr(11,7)) 34 val rs = Mux(isRVC(instr), Mux(brType === BrType.jal, 0.U, instr(11, 7)), instr(19, 15)) 35 val isCall = (brType === BrType.jal && !isRVC(instr) || brType === BrType.jalr) && isLink(rd) // Only for RV64 36 val isRet = brType === BrType.jalr && isLink(rs) && !isCall 37 List(brType, isCall, isRet) 38 } 39} 40 41object BrType { 42 def notBr = "b00".U 43 def branch = "b01".U 44 def jal = "b10".U 45 def jalr = "b11".U 46 def apply() = UInt(2.W) 47} 48 49object ExcType { //TODO:add exctype 50 def notExc = "b000".U 51 def apply() = UInt(3.W) 52} 53 54class PreDecodeInfo extends Bundle { // 8 bit 55 val isRVC = Bool() 56 val brType = UInt(2.W) 57 val isCall = Bool() 58 val isRet = Bool() 59 val excType = UInt(3.W) 60 def isBr = brType === BrType.branch 61 def isJal = brType === BrType.jal 62 def isJalr = brType === BrType.jalr 63 def notCFI = brType === BrType.notBr 64} 65 66class PreDecodeInfoForDebug(val usePerf: Boolean = true) extends Bundle { 67 val isRVC = if (usePerf) Bool() else UInt(0.W) 68 val brType = if (usePerf) UInt(2.W) else UInt(0.W) 69 val isCall = if (usePerf) Bool() else UInt(0.W) 70 val isRet = if (usePerf) Bool() else UInt(0.W) 71 val excType = if (usePerf) UInt(3.W) else UInt(0.W) 72 def isBr = brType === BrType.branch 73 def isJal = brType === BrType.jal 74 def isJalr = brType === BrType.jalr 75 def notCFI = brType === BrType.notBr 76} 77 78class PreDecodeResp(implicit p: Parameters) extends XSBundle with HasIFUConst { 79 val instrs = Vec(PredictWidth, UInt(32.W)) 80 val pc = Vec(PredictWidth, UInt(VAddrBits.W)) 81 val mask = UInt(PredictWidth.W) 82 // one for the first bank 83 val lastHalf = Bool() 84 val pd = Vec(PredictWidth, (new PreDecodeInfo)) 85} 86 87class PreDecode(implicit p: Parameters) extends XSModule with HasPdconst with HasIFUConst { 88 val io = IO(new Bundle() { 89 val in = Input(new ICacheResp) 90 val prev = Flipped(ValidIO(UInt(16.W))) 91 val prev_pc = Input(UInt(VAddrBits.W)) 92 val out = Output(new PreDecodeResp) 93 }) 94 95 val data = io.in.data 96 val mask = io.in.mask 97 98 val packetAlignedPC = packetAligned(io.in.pc) 99 val packetOffset = offsetInPacket(io.in.pc) 100 101 val firstValidIdx = packetOffset // io.prev.valid should only occur with firstValidIdx = 0 102 XSError(firstValidIdx =/= 0.U && io.prev.valid && HasCExtension.B, p"pc:${io.in.pc}, mask:${io.in.mask}, prevhalfInst valid occurs on unaligned fetch packet\n") 103 104 val instsMask = Wire(Vec(PredictWidth, Bool())) 105 val instsEndMask = Wire(Vec(PredictWidth, Bool())) 106 107 val rawInsts = if (HasCExtension) { 108 VecInit((0 until PredictWidth).map(i => if (i == PredictWidth-1) Cat(0.U(16.W), data(i*16+15, i*16)) 109 else data(i*16+31, i*16))) 110 } else { 111 VecInit((0 until PredictWidth).map(i => data(i*32+31, i*32))) 112 } 113 114 for (i <- 0 until PredictWidth) { 115 val inst = WireInit(rawInsts(i)) 116 val validStart = Wire(Bool()) // is the beginning of a valid inst 117 val validEnd = Wire(Bool()) // is the end of a valid inst 118 119 val isFirstInPacket = i.U === firstValidIdx 120 val isLastInPacket = (i == PredictWidth-1).B 121 val currentRVC = isRVC(inst) && HasCExtension.B 122 123 val lastIsValidEnd = (if (i == 0) { !io.prev.valid } else { instsEndMask(i-1) || isFirstInPacket }) || !HasCExtension.B 124 125 inst := (if (HasCExtension) 126 Mux(io.prev.valid && i.U === 0.U, 127 Cat(rawInsts(i)(15,0), io.prev.bits), 128 rawInsts(i)) 129 else 130 rawInsts(i)) 131 132 // when disable rvc, every 4 bytes should be an inst 133 validStart := lastIsValidEnd && !(isLastInPacket && !currentRVC) || !HasCExtension.B 134 validEnd := validStart && currentRVC || !validStart && !(isLastInPacket && !currentRVC) || !HasCExtension.B 135 136 val currentLastHalf = lastIsValidEnd && (isLastInPacket && !currentRVC) && HasCExtension.B 137 138 instsMask(i) := (if (i == 0) Mux(io.prev.valid, validEnd, validStart) else validStart) 139 instsEndMask(i) := validEnd 140 141 val brType::isCall::isRet::Nil = brInfo(inst) 142 io.out.pd(i).isRVC := currentRVC 143 io.out.pd(i).brType := brType 144 io.out.pd(i).isCall := isCall 145 io.out.pd(i).isRet := isRet 146 io.out.pd(i).excType := ExcType.notExc 147 io.out.instrs(i) := inst 148 io.out.pc(i) := Mux(io.prev.valid && HasCExtension.B && (i==0).B, io.prev_pc, Cat(packetIdx(io.in.pc), (i << instOffsetBits).U(log2Ceil(packetBytes).W))) 149 150 if (i == PredictWidth-1) { io.out.lastHalf := currentLastHalf } 151 } 152 io.out.mask := instsMask.asUInt & mask 153 154 for (i <- 0 until PredictWidth) { 155 XSDebug(true.B, 156 p"instr ${Hexadecimal(io.out.instrs(i))}, " + 157 p"mask ${Binary(instsMask(i))}, " + 158 p"endMask ${Binary(instsEndMask(i))}, " + 159 p"pc ${Hexadecimal(io.out.pc(i))}, " + 160 p"isRVC ${Binary(io.out.pd(i).isRVC)}, " + 161 p"brType ${Binary(io.out.pd(i).brType)}, " + 162 p"isRet ${Binary(io.out.pd(i).isRet)}, " + 163 p"isCall ${Binary(io.out.pd(i).isCall)}\n" 164 ) 165 } 166} 167 168class RVCExpander(implicit p: Parameters) extends XSModule { 169 val io = IO(new Bundle { 170 val in = Input(UInt(32.W)) 171 val out = Output(new ExpandedInstruction) 172 }) 173 174 if (HasCExtension) { 175 io.out := new RVCDecoder(io.in, XLEN).decode 176 } else { 177 io.out := new RVCDecoder(io.in, XLEN).passthrough 178 } 179} 180