1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.exu._ 23import xiangshan.backend.dispatch.DispatchParameters 24import xiangshan.cache.DCacheParameters 25import xiangshan.cache.prefetch._ 26import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 27import xiangshan.frontend.icache.ICacheParameters 28import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 29import freechips.rocketchip.diplomacy.AddressSet 30import system.SoCParamsKey 31import huancun._ 32import huancun.debug._ 33import coupledL2._ 34import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 35 36import scala.math.min 37 38case object XSTileKey extends Field[Seq[XSCoreParameters]] 39 40case object XSCoreParamsKey extends Field[XSCoreParameters] 41 42case class XSCoreParameters 43( 44 HasPrefetch: Boolean = false, 45 HartId: Int = 0, 46 XLEN: Int = 64, 47 HasMExtension: Boolean = true, 48 HasCExtension: Boolean = true, 49 HasDiv: Boolean = true, 50 HasICache: Boolean = true, 51 HasDCache: Boolean = true, 52 AddrBits: Int = 64, 53 VAddrBits: Int = 39, 54 HasFPU: Boolean = true, 55 HasCustomCSRCacheOp: Boolean = true, 56 FetchWidth: Int = 8, 57 AsidLength: Int = 16, 58 EnableBPU: Boolean = true, 59 EnableBPD: Boolean = true, 60 EnableRAS: Boolean = true, 61 EnableLB: Boolean = false, 62 EnableLoop: Boolean = true, 63 EnableSC: Boolean = true, 64 EnbaleTlbDebug: Boolean = false, 65 EnableJal: Boolean = false, 66 EnableFauFTB: Boolean = true, 67 UbtbGHRLength: Int = 4, 68 // HistoryLength: Int = 512, 69 EnableGHistDiff: Boolean = true, 70 EnableCommitGHistDiff: Boolean = true, 71 UbtbSize: Int = 256, 72 FtbSize: Int = 2048, 73 RasSize: Int = 32, 74 CacheLineSize: Int = 512, 75 FtbWays: Int = 4, 76 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 77 // Sets Hist Tag 78 // Seq(( 2048, 2, 8), 79 // ( 2048, 9, 8), 80 // ( 2048, 13, 8), 81 // ( 2048, 20, 8), 82 // ( 2048, 26, 8), 83 // ( 2048, 44, 8), 84 // ( 2048, 73, 8), 85 // ( 2048, 256, 8)), 86 Seq(( 4096, 8, 8), 87 ( 4096, 13, 8), 88 ( 4096, 32, 8), 89 ( 4096, 119, 8)), 90 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 91 // Sets Hist Tag 92 Seq(( 256, 4, 9), 93 ( 256, 8, 9), 94 ( 512, 13, 9), 95 ( 512, 16, 9), 96 ( 512, 32, 9)), 97 SCNRows: Int = 512, 98 SCNTables: Int = 4, 99 SCCtrBits: Int = 6, 100 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 101 numBr: Int = 2, 102 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 103 ((resp_in: BranchPredictionResp, p: Parameters) => { 104 val ftb = Module(new FTB()(p)) 105 val ubtb =Module(new FauFTB()(p)) 106 // val bim = Module(new BIM()(p)) 107 val tage = Module(new Tage_SC()(p)) 108 val ras = Module(new RAS()(p)) 109 val ittage = Module(new ITTage()(p)) 110 val preds = Seq(ubtb, tage, ftb, ittage, ras) 111 preds.map(_.io := DontCare) 112 113 // ubtb.io.resp_in(0) := resp_in 114 // bim.io.resp_in(0) := ubtb.io.resp 115 // btb.io.resp_in(0) := bim.io.resp 116 // tage.io.resp_in(0) := btb.io.resp 117 // loop.io.resp_in(0) := tage.io.resp 118 ubtb.io.in.bits.resp_in(0) := resp_in 119 tage.io.in.bits.resp_in(0) := ubtb.io.out 120 ftb.io.in.bits.resp_in(0) := tage.io.out 121 ittage.io.in.bits.resp_in(0) := ftb.io.out 122 ras.io.in.bits.resp_in(0) := ittage.io.out 123 124 (preds, ras.io.out) 125 }), 126 IBufSize: Int = 48, 127 DecodeWidth: Int = 6, 128 RenameWidth: Int = 6, 129 CommitWidth: Int = 6, 130 EnableRenameSnapshot: Boolean = true, 131 RenameSnapshotNum: Int = 4, 132 FtqSize: Int = 64, 133 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 134 IssQueSize: Int = 16, 135 NRPhyRegs: Int = 192, 136 VirtualLoadQueueSize: Int = 80, 137 LoadQueueRARSize: Int = 80, 138 LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2. 139 RollbackGroupSize: Int = 8, 140 LoadQueueReplaySize: Int = 72, 141 LoadUncacheBufferSize: Int = 20, 142 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 143 StoreQueueSize: Int = 64, 144 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 145 StoreQueueForwardWithMask: Boolean = true, 146 VlsQueueSize: Int = 8, 147 RobSize: Int = 256, 148 dpParams: DispatchParameters = DispatchParameters( 149 IntDqSize = 16, 150 FpDqSize = 16, 151 LsDqSize = 16, 152 IntDqDeqWidth = 4, 153 FpDqDeqWidth = 4, 154 LsDqDeqWidth = 4 155 ), 156 exuParameters: ExuParameters = ExuParameters( 157 JmpCnt = 1, 158 AluCnt = 4, 159 MulCnt = 0, 160 MduCnt = 2, 161 FmacCnt = 4, 162 FmiscCnt = 2, 163 FmiscDivSqrtCnt = 0, 164 LduCnt = 2, 165 StuCnt = 2 166 ), 167 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 168 LoadPipelineWidth: Int = 2, 169 StorePipelineWidth: Int = 2, 170 VecMemSrcInWidth: Int = 2, 171 VecMemInstWbWidth: Int = 1, 172 VecMemDispatchWidth: Int = 1, 173 StoreBufferSize: Int = 16, 174 StoreBufferThreshold: Int = 7, 175 EnsbufferWidth: Int = 2, 176 UncacheBufferSize: Int = 4, 177 EnableLoadToLoadForward: Boolean = true, 178 EnableFastForward: Boolean = true, 179 EnableLdVioCheckAfterReset: Boolean = true, 180 EnableSoftPrefetchAfterReset: Boolean = true, 181 EnableCacheErrorAfterReset: Boolean = true, 182 EnableDCacheWPU: Boolean = false, 183 EnableAccurateLoadError: Boolean = true, 184 EnableUncacheWriteOutstanding: Boolean = false, 185 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 186 ReSelectLen: Int = 7, // load replay queue replay select counter len 187 itlbParameters: TLBParameters = TLBParameters( 188 name = "itlb", 189 fetchi = true, 190 useDmode = false, 191 normalNWays = 32, 192 normalReplacer = Some("plru"), 193 superNWays = 4, 194 superReplacer = Some("plru") 195 ), 196 itlbPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 197 ipmpPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 198 ldtlbParameters: TLBParameters = TLBParameters( 199 name = "ldtlb", 200 normalNSets = 64, 201 normalNWays = 1, 202 normalAssociative = "sa", 203 normalReplacer = Some("setplru"), 204 superNWays = 16, 205 normalAsVictim = true, 206 outReplace = false, 207 partialStaticPMP = true, 208 outsideRecvFlush = true, 209 saveLevel = true 210 ), 211 sttlbParameters: TLBParameters = TLBParameters( 212 name = "sttlb", 213 normalNSets = 64, 214 normalNWays = 1, 215 normalAssociative = "sa", 216 normalReplacer = Some("setplru"), 217 superNWays = 16, 218 normalAsVictim = true, 219 outReplace = false, 220 partialStaticPMP = true, 221 outsideRecvFlush = true, 222 saveLevel = true 223 ), 224 pftlbParameters: TLBParameters = TLBParameters( 225 name = "pftlb", 226 normalNSets = 64, 227 normalNWays = 1, 228 normalAssociative = "sa", 229 normalReplacer = Some("setplru"), 230 superNWays = 16, 231 normalAsVictim = true, 232 outReplace = false, 233 partialStaticPMP = true, 234 outsideRecvFlush = true, 235 saveLevel = true 236 ), 237 refillBothTlb: Boolean = false, 238 btlbParameters: TLBParameters = TLBParameters( 239 name = "btlb", 240 normalNSets = 1, 241 normalNWays = 64, 242 superNWays = 4, 243 ), 244 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 245 NumPerfCounters: Int = 16, 246 icacheParameters: ICacheParameters = ICacheParameters( 247 tagECC = Some("parity"), 248 dataECC = Some("parity"), 249 replacer = Some("setplru"), 250 nMissEntries = 2, 251 nProbeEntries = 2, 252 nPrefetchEntries = 12, 253 nPrefBufferEntries = 64, 254 hasPrefetch = true, 255 ), 256 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 257 tagECC = Some("secded"), 258 dataECC = Some("secded"), 259 replacer = Some("setplru"), 260 nMissEntries = 16, 261 nProbeEntries = 8, 262 nReleaseEntries = 18 263 )), 264 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 265 name = "l2", 266 ways = 8, 267 sets = 1024, // default 512KB L2 268 prefetch = Some(coupledL2.prefetch.PrefetchReceiverParams()) 269 )), 270 L2NBanks: Int = 1, 271 usePTWRepeater: Boolean = false, 272 softTLB: Boolean = false, // dpi-c l1tlb debug only 273 softPTW: Boolean = false, // dpi-c l2tlb debug only 274 softPTWDelay: Int = 1 275){ 276 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 277 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 278 279 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 280 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg) ++ Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg) 281 282 val intExuConfigs = (Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++ 283 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg) 284 285 val fpExuConfigs = 286 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 287 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 288 289 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 290} 291 292case object DebugOptionsKey extends Field[DebugOptions] 293 294case class DebugOptions 295( 296 FPGAPlatform: Boolean = false, 297 EnableDifftest: Boolean = false, 298 AlwaysBasicDiff: Boolean = true, 299 EnableDebug: Boolean = false, 300 EnablePerfDebug: Boolean = true, 301 UseDRAMSim: Boolean = false, 302 EnableConstantin: Boolean = false, 303 EnableChiselDB: Boolean = false, 304 AlwaysBasicDB: Boolean = true, 305) 306 307trait HasXSParameter { 308 309 implicit val p: Parameters 310 311 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 312 313 val coreParams = p(XSCoreParamsKey) 314 val env = p(DebugOptionsKey) 315 316 val XLEN = coreParams.XLEN 317 val minFLen = 32 318 val fLen = 64 319 def xLen = XLEN 320 321 val HasMExtension = coreParams.HasMExtension 322 val HasCExtension = coreParams.HasCExtension 323 val HasDiv = coreParams.HasDiv 324 val HasIcache = coreParams.HasICache 325 val HasDcache = coreParams.HasDCache 326 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 327 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 328 val AsidLength = coreParams.AsidLength 329 val ReSelectLen = coreParams.ReSelectLen 330 val AddrBytes = AddrBits / 8 // unused 331 val DataBits = XLEN 332 val DataBytes = DataBits / 8 333 val HasFPU = coreParams.HasFPU 334 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 335 val FetchWidth = coreParams.FetchWidth 336 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 337 val EnableBPU = coreParams.EnableBPU 338 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 339 val EnableRAS = coreParams.EnableRAS 340 val EnableLB = coreParams.EnableLB 341 val EnableLoop = coreParams.EnableLoop 342 val EnableSC = coreParams.EnableSC 343 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 344 val HistoryLength = coreParams.HistoryLength 345 val EnableGHistDiff = coreParams.EnableGHistDiff 346 val EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 347 val UbtbGHRLength = coreParams.UbtbGHRLength 348 val UbtbSize = coreParams.UbtbSize 349 val EnableFauFTB = coreParams.EnableFauFTB 350 val FtbSize = coreParams.FtbSize 351 val FtbWays = coreParams.FtbWays 352 val RasSize = coreParams.RasSize 353 354 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 355 coreParams.branchPredictor(resp_in, p) 356 } 357 val numBr = coreParams.numBr 358 val TageTableInfos = coreParams.TageTableInfos 359 val TageBanks = coreParams.numBr 360 val SCNRows = coreParams.SCNRows 361 val SCCtrBits = coreParams.SCCtrBits 362 val SCHistLens = coreParams.SCHistLens 363 val SCNTables = coreParams.SCNTables 364 365 val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 366 case ((n, cb), h) => (n, cb, h) 367 } 368 val ITTageTableInfos = coreParams.ITTageTableInfos 369 type FoldedHistoryInfo = Tuple2[Int, Int] 370 val foldedGHistInfos = 371 (TageTableInfos.map{ case (nRows, h, t) => 372 if (h > 0) 373 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 374 else 375 Set[FoldedHistoryInfo]() 376 }.reduce(_++_).toSet ++ 377 SCTableInfos.map{ case (nRows, _, h) => 378 if (h > 0) 379 Set((h, min(log2Ceil(nRows/TageBanks), h))) 380 else 381 Set[FoldedHistoryInfo]() 382 }.reduce(_++_).toSet ++ 383 ITTageTableInfos.map{ case (nRows, h, t) => 384 if (h > 0) 385 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 386 else 387 Set[FoldedHistoryInfo]() 388 }.reduce(_++_) ++ 389 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 390 ).toList 391 392 393 394 val CacheLineSize = coreParams.CacheLineSize 395 val CacheLineHalfWord = CacheLineSize / 16 396 val ExtHistoryLength = HistoryLength + 64 397 val IBufSize = coreParams.IBufSize 398 val DecodeWidth = coreParams.DecodeWidth 399 val RenameWidth = coreParams.RenameWidth 400 val CommitWidth = coreParams.CommitWidth 401 val EnableRenameSnapshot = coreParams.EnableRenameSnapshot 402 val RenameSnapshotNum = coreParams.RenameSnapshotNum 403 val FtqSize = coreParams.FtqSize 404 val IssQueSize = coreParams.IssQueSize 405 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 406 val NRPhyRegs = coreParams.NRPhyRegs 407 val PhyRegIdxWidth = log2Up(NRPhyRegs) 408 val RobSize = coreParams.RobSize 409 val IntRefCounterWidth = log2Ceil(RobSize) 410 val VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 411 val LoadQueueRARSize = coreParams.LoadQueueRARSize 412 val LoadQueueRAWSize = coreParams.LoadQueueRAWSize 413 val RollbackGroupSize = coreParams.RollbackGroupSize 414 val LoadQueueReplaySize = coreParams.LoadQueueReplaySize 415 val LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 416 val LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 417 val StoreQueueSize = coreParams.StoreQueueSize 418 val StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 419 val StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 420 val VlsQueueSize = coreParams.VlsQueueSize 421 val dpParams = coreParams.dpParams 422 val exuParameters = coreParams.exuParameters 423 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 424 val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts 425 val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt 426 val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt 427 val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt 428 val LoadPipelineWidth = coreParams.LoadPipelineWidth 429 val StorePipelineWidth = coreParams.StorePipelineWidth 430 val VecMemSrcInWidth = coreParams.VecMemSrcInWidth 431 val VecMemInstWbWidth = coreParams.VecMemInstWbWidth 432 val VecMemDispatchWidth = coreParams.VecMemDispatchWidth 433 val StoreBufferSize = coreParams.StoreBufferSize 434 val StoreBufferThreshold = coreParams.StoreBufferThreshold 435 val EnsbufferWidth = coreParams.EnsbufferWidth 436 val UncacheBufferSize = coreParams.UncacheBufferSize 437 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 438 val EnableFastForward = coreParams.EnableFastForward 439 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 440 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 441 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 442 val EnableDCacheWPU = coreParams.EnableDCacheWPU 443 val EnableAccurateLoadError = coreParams.EnableAccurateLoadError 444 val EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 445 val asidLen = coreParams.MMUAsidLen 446 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 447 val refillBothTlb = coreParams.refillBothTlb 448 val itlbParams = coreParams.itlbParameters 449 val ldtlbParams = coreParams.ldtlbParameters 450 val sttlbParams = coreParams.sttlbParameters 451 val pftlbParams = coreParams.pftlbParameters 452 val btlbParams = coreParams.btlbParameters 453 val l2tlbParams = coreParams.l2tlbParameters 454 val NumPerfCounters = coreParams.NumPerfCounters 455 456 val NumRs = (exuParameters.JmpCnt+1)/2 + (exuParameters.AluCnt+1)/2 + (exuParameters.MulCnt+1)/2 + 457 (exuParameters.MduCnt+1)/2 + (exuParameters.FmacCnt+1)/2 + + (exuParameters.FmiscCnt+1)/2 + 458 (exuParameters.FmiscDivSqrtCnt+1)/2 + (exuParameters.LduCnt+1)/2 + 459 (exuParameters.StuCnt+1)/2 + (exuParameters.StuCnt+1)/2 460 461 val instBytes = if (HasCExtension) 2 else 4 462 val instOffsetBits = log2Ceil(instBytes) 463 464 val icacheParameters = coreParams.icacheParameters 465 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 466 467 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 468 // for constrained LR/SC loop 469 val LRSCCycles = 64 470 // for lr storm 471 val LRSCBackOff = 8 472 473 // cache hierarchy configurations 474 val l1BusDataWidth = 256 475 476 // load violation predict 477 val ResetTimeMax2Pow = 20 //1078576 478 val ResetTimeMin2Pow = 10 //1024 479 // wait table parameters 480 val WaitTableSize = 1024 481 val MemPredPCWidth = log2Up(WaitTableSize) 482 val LWTUse2BitCounter = true 483 // store set parameters 484 val SSITSize = WaitTableSize 485 val LFSTSize = 32 486 val SSIDWidth = log2Up(LFSTSize) 487 val LFSTWidth = 4 488 val StoreSetEnable = true // LWT will be disabled if SS is enabled 489 val LFSTEnable = false 490 val loadExuConfigs = coreParams.loadExuConfigs 491 val storeExuConfigs = coreParams.storeExuConfigs 492 493 val intExuConfigs = coreParams.intExuConfigs 494 495 val fpExuConfigs = coreParams.fpExuConfigs 496 497 val exuConfigs = coreParams.exuConfigs 498 499 val PCntIncrStep: Int = 6 500 val numPCntHc: Int = 25 501 val numPCntPtw: Int = 19 502 503 val numCSRPCntFrontend = 8 504 val numCSRPCntCtrl = 8 505 val numCSRPCntLsu = 8 506 val numCSRPCntHc = 5 507} 508