xref: /XiangShan/src/main/scala/xiangshan/mem/prefetch/L1PrefetchInterface.scala (revision b8b991d636e3eae0d6cc2e36846166652699f0c2) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package xiangshan.mem
18
19import chipsalliance.rocketchip.config.Parameters
20import chisel3._
21import chisel3.util._
22import utils._
23import utility._
24import xiangshan.ExceptionNO._
25import xiangshan._
26import xiangshan.backend.fu.PMPRespBundle
27import xiangshan.cache._
28import xiangshan.cache.mmu.{TlbCmd, TlbReq, TlbRequestIO, TlbResp}
29
30class L1PrefetchReq (implicit p: Parameters) extends XSBundle with HasDCacheParameters{
31  val paddr = UInt(PAddrBits.W)
32  val alias = UInt(2.W)
33  val confidence = UInt(1.W)
34  val is_store = Bool()
35
36  // only index bit is used, do not use tag
37  def getVaddr(): UInt = {
38    Cat(alias, paddr(DCacheSameVPAddrLength-1, 0))
39  }
40
41  // when l1 cache prefetch req arrives at load unit:
42  // if (confidence == 1)
43  //   override load unit 2 load req
44  // else if (load unit 1/2 is available)
45  //   send prefetch req
46  // else
47  //   report prefetch !ready
48}
49
50class L1PrefetchHint (implicit p: Parameters) extends XSBundle with HasDCacheParameters{
51  val loadbusy = Bool()
52  val missqbusy = Bool()
53}
54
55class L1PrefetchFuzzer(implicit p: Parameters) extends DCacheModule{
56  val io = IO(new Bundle() {
57    // prefetch req interface
58    val req = Decoupled(new L1PrefetchReq())
59    // for fuzzer address gen
60    val vaddr = Input(UInt(VAddrBits.W))
61    val paddr = Input(UInt(PAddrBits.W))
62  })
63
64  // prefetch req queue is not provided, prefetcher must maintain its
65  // own prefetch req queue.
66  val rand_offset = LFSR64(seed=Some(123L))(5,0) << 6
67  val rand_addr_select = LFSR64(seed=Some(567L))(3,0) === 0.U
68
69  // use valid vaddr and paddr
70  val rand_vaddr = DelayN(io.vaddr, 2)
71  val rand_paddr = DelayN(io.paddr, 2)
72
73  io.req.bits.paddr := 0x80000000L.U + rand_offset
74  io.req.bits.alias := io.req.bits.paddr(13,12)
75  io.req.bits.confidence := LFSR64(seed=Some(789L))(4,0) === 0.U
76  io.req.bits.is_store := LFSR64(seed=Some(890L))(4,0) === 0.U
77  io.req.valid := LFSR64(seed=Some(901L))(3,0) === 0.U
78}