1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.cache.mmu 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import xiangshan._ 23import xiangshan.cache.{HasDCacheParameters, MemoryOpConstants} 24import utils._ 25import utility._ 26import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 27import freechips.rocketchip.tilelink._ 28 29 30case class TLBParameters 31( 32 name: String = "none", 33 fetchi: Boolean = false, // TODO: remove it 34 fenceDelay: Int = 2, 35 useDmode: Boolean = true, 36 normalNSets: Int = 1, // when da or sa 37 normalNWays: Int = 8, // when fa or sa 38 superNSets: Int = 1, 39 superNWays: Int = 2, 40 normalReplacer: Option[String] = Some("random"), 41 superReplacer: Option[String] = Some("plru"), 42 normalAssociative: String = "fa", // "fa", "sa", "da", "sa" is not supported 43 superAssociative: String = "fa", // must be fa 44 normalAsVictim: Boolean = false, // when get replace from fa, store it into sram 45 outReplace: Boolean = false, 46 partialStaticPMP: Boolean = false, // partial static pmp result stored in entries 47 outsideRecvFlush: Boolean = false, // if outside moudle waiting for tlb recv flush pipe 48 saveLevel: Boolean = false 49) 50 51case class L2TLBParameters 52( 53 name: String = "l2tlb", 54 // l1 55 l1Size: Int = 16, 56 l1Associative: String = "fa", 57 l1Replacer: Option[String] = Some("plru"), 58 // l2 59 l2nSets: Int = 32, 60 l2nWays: Int = 2, 61 l2Replacer: Option[String] = Some("setplru"), 62 // l3 63 l3nSets: Int = 128, 64 l3nWays: Int = 4, 65 l3Replacer: Option[String] = Some("setplru"), 66 // sp 67 spSize: Int = 16, 68 spReplacer: Option[String] = Some("plru"), 69 // filter 70 ifilterSize: Int = 4, 71 dfilterSize: Int = 8, 72 // miss queue, add more entries than 'must require' 73 // 0 for easier bug trigger, please set as big as u can, 8 maybe 74 missqueueExtendSize: Int = 0, 75 // llptw 76 llptwsize: Int = 6, 77 // way size 78 blockBytes: Int = 64, 79 // prefetch 80 enablePrefetch: Boolean = true, 81 // ecc 82 ecc: Option[String] = Some("secded") 83) 84 85trait HasTlbConst extends HasXSParameter { 86 val Level = 3 87 88 val offLen = 12 89 val ppnLen = PAddrBits - offLen 90 val vpnnLen = 9 91 val vpnLen = VAddrBits - offLen 92 val flagLen = 8 93 val pteResLen = XLEN - 44 - 2 - flagLen 94 val ppnHignLen = 44 - ppnLen 95 96 val tlbcontiguous = 8 97 val sectortlbwidth = log2Up(tlbcontiguous) 98 val sectorppnLen = ppnLen - sectortlbwidth 99 val sectorvpnLen = vpnLen - sectortlbwidth 100 101 val sramSinglePort = true 102 103 val timeOutThreshold = 10000 104 105 def get_pn(addr: UInt) = { 106 require(addr.getWidth > offLen) 107 addr(addr.getWidth-1, offLen) 108 } 109 def get_off(addr: UInt) = { 110 require(addr.getWidth > offLen) 111 addr(offLen-1, 0) 112 } 113 114 def get_set_idx(vpn: UInt, nSets: Int): UInt = { 115 require(nSets >= 1) 116 vpn(log2Up(nSets)-1, 0) 117 } 118 119 def drop_set_idx(vpn: UInt, nSets: Int): UInt = { 120 require(nSets >= 1) 121 require(vpn.getWidth > log2Ceil(nSets)) 122 vpn(vpn.getWidth-1, log2Ceil(nSets)) 123 } 124 125 def drop_set_equal(vpn1: UInt, vpn2: UInt, nSets: Int): Bool = { 126 require(nSets >= 1) 127 require(vpn1.getWidth == vpn2.getWidth) 128 if (vpn1.getWidth <= log2Ceil(nSets)) { 129 true.B 130 } else { 131 drop_set_idx(vpn1, nSets) === drop_set_idx(vpn2, nSets) 132 } 133 } 134 135 def replaceWrapper(v: UInt, lruIdx: UInt): UInt = { 136 val width = v.getWidth 137 val emptyIdx = ParallelPriorityMux((0 until width).map( i => (!v(i), i.U(log2Up(width).W)))) 138 val full = Cat(v).andR 139 Mux(full, lruIdx, emptyIdx) 140 } 141 142 def replaceWrapper(v: Seq[Bool], lruIdx: UInt): UInt = { 143 replaceWrapper(VecInit(v).asUInt, lruIdx) 144 } 145 146 implicit def ptwresp_to_tlbperm(ptwResp: PtwSectorRespwithMemIdx): TlbPermBundle = { 147 val tp = Wire(new TlbPermBundle) 148 val ptePerm = ptwResp.entry.perm.get.asTypeOf(new PtePermBundle().cloneType) 149 tp.pf := ptwResp.pf 150 tp.af := ptwResp.af 151 tp.d := ptePerm.d 152 tp.a := ptePerm.a 153 tp.g := ptePerm.g 154 tp.u := ptePerm.u 155 tp.x := ptePerm.x 156 tp.w := ptePerm.w 157 tp.r := ptePerm.r 158 tp.pm := DontCare 159 tp 160 } 161} 162 163trait HasPtwConst extends HasTlbConst with MemoryOpConstants{ 164 val PtwWidth = 2 165 val sourceWidth = { if (l2tlbParams.enablePrefetch) PtwWidth + 1 else PtwWidth} 166 val prefetchID = PtwWidth 167 168 val blockBits = l2tlbParams.blockBytes * 8 169 170 val bPtwWidth = log2Up(PtwWidth) 171 val bSourceWidth = log2Up(sourceWidth) 172 // ptwl1: fully-associated 173 val PtwL1TagLen = vpnnLen 174 175 /* +-------+----------+-------------+ 176 * | Tag | SetIdx | SectorIdx | 177 * +-------+----------+-------------+ 178 */ 179 // ptwl2: 8-way group-associated 180 val l2tlbParams.l2nWays = l2tlbParams.l2nWays 181 val PtwL2SetNum = l2tlbParams.l2nSets 182 val PtwL2SectorSize = blockBits / XLEN 183 val PtwL2IdxLen = log2Up(PtwL2SetNum * PtwL2SectorSize) 184 val PtwL2SectorIdxLen = log2Up(PtwL2SectorSize) 185 val PtwL2SetIdxLen = log2Up(PtwL2SetNum) 186 val PtwL2TagLen = vpnnLen * 2 - PtwL2IdxLen 187 188 // ptwl3: 16-way group-associated 189 val l2tlbParams.l3nWays = l2tlbParams.l3nWays 190 val PtwL3SetNum = l2tlbParams.l3nSets 191 val PtwL3SectorSize = blockBits / XLEN 192 val PtwL3IdxLen = log2Up(PtwL3SetNum * PtwL3SectorSize) 193 val PtwL3SectorIdxLen = log2Up(PtwL3SectorSize) 194 val PtwL3SetIdxLen = log2Up(PtwL3SetNum) 195 val PtwL3TagLen = vpnnLen * 3 - PtwL3IdxLen 196 197 // super page, including 1GB and 2MB page 198 val SPTagLen = vpnnLen * 2 199 200 // miss queue 201 val MissQueueSize = l2tlbParams.ifilterSize + l2tlbParams.dfilterSize 202 val MemReqWidth = l2tlbParams.llptwsize + 1 203 val FsmReqID = l2tlbParams.llptwsize 204 val bMemID = log2Up(MemReqWidth) 205 206 def genPtwL2Idx(vpn: UInt) = { 207 (vpn(vpnLen - 1, vpnnLen))(PtwL2IdxLen - 1, 0) 208 } 209 210 def genPtwL2SectorIdx(vpn: UInt) = { 211 genPtwL2Idx(vpn)(PtwL2SectorIdxLen - 1, 0) 212 } 213 214 def genPtwL2SetIdx(vpn: UInt) = { 215 genPtwL2Idx(vpn)(PtwL2SetIdxLen + PtwL2SectorIdxLen - 1, PtwL2SectorIdxLen) 216 } 217 218 def genPtwL3Idx(vpn: UInt) = { 219 vpn(PtwL3IdxLen - 1, 0) 220 } 221 222 def genPtwL3SectorIdx(vpn: UInt) = { 223 genPtwL3Idx(vpn)(PtwL3SectorIdxLen - 1, 0) 224 } 225 226 def dropL3SectorBits(vpn: UInt) = { 227 vpn(vpn.getWidth-1, PtwL3SectorIdxLen) 228 } 229 230 def genPtwL3SetIdx(vpn: UInt) = { 231 genPtwL3Idx(vpn)(PtwL3SetIdxLen + PtwL3SectorIdxLen - 1, PtwL3SectorIdxLen) 232 } 233 234 def MakeAddr(ppn: UInt, off: UInt) = { 235 require(off.getWidth == 9) 236 Cat(ppn, off, 0.U(log2Up(XLEN/8).W))(PAddrBits-1, 0) 237 } 238 239 def getVpnn(vpn: UInt, idx: Int): UInt = { 240 vpn(vpnnLen*(idx+1)-1, vpnnLen*idx) 241 } 242 243 def getVpnClip(vpn: UInt, level: Int) = { 244 // level 0 /* vpnn2 */ 245 // level 1 /* vpnn2 * vpnn1 */ 246 // level 2 /* vpnn2 * vpnn1 * vpnn0*/ 247 vpn(vpnLen - 1, (2 - level) * vpnnLen) 248 } 249 250 def get_next_line(vpn: UInt) = { 251 Cat(dropL3SectorBits(vpn) + 1.U, 0.U(PtwL3SectorIdxLen.W)) 252 } 253 254 def same_l2entry(vpn1: UInt, vpn2: UInt) = { 255 vpn1(vpnLen-1, vpnnLen) === vpn2(vpnLen-1, vpnnLen) 256 } 257 258 def from_pre(source: UInt) = { 259 (source === prefetchID.U) 260 } 261 262 def sel_data(data: UInt, index: UInt): UInt = { 263 val inner_data = data.asTypeOf(Vec(data.getWidth / XLEN, UInt(XLEN.W))) 264 inner_data(index) 265 } 266 267 // vpn1 and vpn2 is at same cacheline 268 def dup(vpn1: UInt, vpn2: UInt): Bool = { 269 dropL3SectorBits(vpn1) === dropL3SectorBits(vpn2) 270 } 271 272 273 def printVec[T <: Data](x: Seq[T]): Printable = { 274 (0 until x.length).map(i => p"(${i.U})${x(i)} ").reduce(_+_) 275 } 276} 277