fix(PTW): High bits of GVPN should not be truncated (#4406)

feat(PTWCache): Support a more precise flush for L2 TLB entries (#4390)

In the previous design, since we stored asid/vmid and vaddr information
in SRAM, it was not possible to simply read out all th

feat(PTWCache): Support a more precise flush for L2 TLB entries (#4390)

In the previous design, since we stored asid/vmid and vaddr information
in SRAM, it was not possible to simply read out all the information in a
single cycle for comparison with the parameters of sfence/hfence. As a
result, for L2 TLB entries, we ignored the rs1/rs2 parameters passed by
sfence/hfence and instead flushed all valid entries, regardless of
asid/vmid or vaddr.

However, this caused unnecessary flushing of a large number of entries
during process switching in virtualized environments, leading to L2 TLB
misses after a process switch. This forced the processor to perform a
page table walk in memory again, negatively impacting performance.

In this commit, asid/vmid and vaddr are hashed and stored in the
register file. When an sfence/hfence signal is received, these stored
values are compared against the incoming parameters, allowing for a more
precise TLB flush.

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feat(bitmap/memenc): support memory isolation by bitmap checking and memory encrpty used SM4-XTS (#3980)

- Add bitmap module in MMU for memory isolation
- Add memory encryption module based on AXI p

feat(bitmap/memenc): support memory isolation by bitmap checking and memory encrpty used SM4-XTS (#3980)

- Add bitmap module in MMU for memory isolation
- Add memory encryption module based on AXI protoco
- Can don't using these modules by setting the option `HasMEMencryption`
& `HasBitmapCheck` to false

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feat(Svnapot): support Svnapot extension (#4107)

area(PTWCache): reduce l2tlb entries from 2k to 1k (#4003)

Previous design: l0 32 sets * 8 ways * 8 entries = 2048; l1 8 sets * 4 ways * 8 entries = 512

Modified: l0 32 sets * 4 ways * 8 entries

area(PTWCache): reduce l2tlb entries from 2k to 1k (#4003)

Previous design: l0 32 sets * 8 ways * 8 entries = 2048; l1 8 sets * 4 ways * 8 entries = 512

Modified: l0 32 sets * 4 ways * 8 entries = 1024; l1 8 sets * 2 ways * 8 entries = 256

Performance drops by 0.09% in spec06 with 0.3 coverage.

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feat(pointer masking): support Ssnpm & Smnpm & Smmpm (#3921)

feat(pointer masking): support Ssnpm & Smnpm & Smmpm

fix(L1TLB, RVH): fix the wrong pf because the perm check of fake pte (#3553)

chore(MMUConst): raise time out threshold (#3549)

With CHI enabled and CMN connected, a transaction may easily last over
10,000 cycles. This commit raises the time out threshold of PTW to
100,000

chore(MMUConst): raise time out threshold (#3549)

With CHI enabled and CMN connected, a transaction may easily last over
10,000 cycles. This commit raises the time out threshold of PTW to
100,000 cycles.

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feat(PTWCache): split Page Cache SRAM (#3503)

l0: 32 * 3624 -> 32 * (16 * 228), fill 24 reserved bits
waySplit = 4, dataSplit = 4
l1: 8 * 1560 -> 8 * (8 * 200), fill 40 reserved bits
wayS

feat(PTWCache): split Page Cache SRAM (#3503)

l0: 32 * 3624 -> 32 * (16 * 228), fill 24 reserved bits
waySplit = 4, dataSplit = 4
l1: 8 * 1560 -> 8 * (8 * 200), fill 40 reserved bits
waySplit = 2, dataSplit = 4

also, minimalconfig need different reservedBits (for l0 and l1, 0 & 1),
just for requirement in SplittedSRAM.

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fix(PTW): fix the bug that gpf does't happen when gpaddr high bits check fails in onlyStage2 (#3481)

checking the high bits of gpaddr need according to the mode of hgatp
rather than the mode of vsa

fix(PTW): fix the bug that gpf does't happen when gpaddr high bits check fails in onlyStage2 (#3481)

checking the high bits of gpaddr need according to the mode of hgatp
rather than the mode of vsatp

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svpbmt: add simplified support (#3404)

Only the `pbmt` attribute is added and treated as MMIO when `pbmt` is NC
or IO.

---------

Co-authored-by: ngc7331 <[email protected]>

MMU, RVH: add the check of gpaddr high bits and fix some bugs (#3348)

RVA23: Support Sv48 & Sv48x4 (#3406)

Co-authored-by: Xuan Hu <[email protected]>

build: purge chisel 3 and add deprecation check (#3250)

L2TLB, RVH: change ppnlen from 24 to 29 for the first stage translation in two stage translation (#3121)

The first stage is sv39 and the second stage is sv39x4. Before Xiangshan
realizes H extensio

L2TLB, RVH: change ppnlen from 24 to 29 for the first stage translation in two stage translation (#3121)

The first stage is sv39 and the second stage is sv39x4. Before Xiangshan
realizes H extension, the paddr is 36 bits, so ppnlen is 24 bits. After
Xiangshan realizes H extension, the ppnlen of stage 1 should be 29 bits
because the paddr of stage 1 is gpaddr for host and gpaddr is 41 bits. I
add the gvpnlen to replace the ppnlen of stage 1 in L2TLB.

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Merge branch 'master' into vlsu-merge-master-0504

Parameters: replace val with def in trait HasXSParametes (#2952)

This will make FIR elaboration much faster.

Signed-off-by: Yangyu Chen <[email protected]>

Merge branch 'master' into vlsu-tmp-master

rv64v: implement lsu & lsq vector datapath

Prepare to merge master (#2814)

PTW, PageCache: set ECC disable by default (#2882)

It should be noted that this commit will change SRAM width between ecc
enable and unable.

Merge remote-tracking branch 'upstream/master' into tmp-master

TODO: add gpaddr data path from frontend to backend

RVH: fix the errors after git rebase

PTW: fix a bug about hpaddr which ptw send to hptw

page cache: fix a bug about compare tag with vpn in sp hit check