1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.cache.mmu 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import xiangshan._ 23import xiangshan.cache.{HasDCacheParameters, MemoryOpConstants} 24import utils._ 25import utility._ 26import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 27import freechips.rocketchip.tilelink._ 28 29 30case class TLBParameters 31( 32 name: String = "none", 33 fetchi: Boolean = false, // TODO: remove it 34 fenceDelay: Int = 2, 35 useDmode: Boolean = true, 36 NSets: Int = 1, 37 NWays: Int = 2, 38 Replacer: Option[String] = Some("plru"), 39 Associative: String = "fa", // must be fa 40 outReplace: Boolean = false, 41 partialStaticPMP: Boolean = false, // partial static pmp result stored in entries 42 outsideRecvFlush: Boolean = false, // if outside moudle waiting for tlb recv flush pipe 43 saveLevel: Boolean = false, 44 lgMaxSize: Int = 3 45) 46 47case class L2TLBParameters 48( 49 name: String = "l2tlb", 50 // l1 51 l1Size: Int = 16, 52 l1Associative: String = "fa", 53 l1Replacer: Option[String] = Some("plru"), 54 // l2 55 l2nSets: Int = 8, 56 l2nWays: Int = 4, 57 l2Replacer: Option[String] = Some("setplru"), 58 // l3 59 l3nSets: Int = 32, 60 l3nWays: Int = 8, 61 l3Replacer: Option[String] = Some("setplru"), 62 // sp 63 spSize: Int = 16, 64 spReplacer: Option[String] = Some("plru"), 65 // filter 66 ifilterSize: Int = 8, 67 dfilterSize: Int = 32, 68 // miss queue, add more entries than 'must require' 69 // 0 for easier bug trigger, please set as big as u can, 8 maybe 70 missqueueExtendSize: Int = 0, 71 // llptw 72 llptwsize: Int = 6, 73 // way size 74 blockBytes: Int = 64, 75 // prefetch 76 enablePrefetch: Boolean = true, 77 // ecc 78 ecc: Option[String] = Some("secded"), 79 // enable ecc 80 enablePTWECC: Boolean = false 81) 82 83trait HasTlbConst extends HasXSParameter { 84 val Level = 3 85 86 val offLen = 12 87 val ppnLen = PAddrBits - offLen 88 val vpnnLen = 9 89 val extendVpnnBits = if (HasHExtension) 2 else 0 90 val vpnLen = VAddrBits - offLen // when opening H extention, vpnlen broaden two bits 91 val flagLen = 8 92 val pteResLen = XLEN - 44 - 2 - flagLen 93 val ppnHignLen = 44 - ppnLen 94 95 val tlbcontiguous = 8 96 val sectortlbwidth = log2Up(tlbcontiguous) 97 val sectorppnLen = ppnLen - sectortlbwidth 98 val sectorvpnLen = vpnLen - sectortlbwidth 99 100 val loadfiltersize = 16 // 4*3(LduCnt:2 + HyuCnt:1) + 4(prefetch:1) 101 val storefiltersize = if (StorePipelineWidth >= 3) 16 else 8 102 val prefetchfiltersize = 8 103 104 val sramSinglePort = true 105 106 val timeOutThreshold = 10000 107 108 def noS2xlate = "b00".U 109 def allStage = "b11".U 110 def onlyStage1 = "b01".U 111 def onlyStage2 = "b10".U 112 113 def get_pn(addr: UInt) = { 114 require(addr.getWidth > offLen) 115 addr(addr.getWidth-1, offLen) 116 } 117 def get_off(addr: UInt) = { 118 require(addr.getWidth > offLen) 119 addr(offLen-1, 0) 120 } 121 122 def get_set_idx(vpn: UInt, nSets: Int): UInt = { 123 require(nSets >= 1) 124 vpn(log2Up(nSets)-1, 0) 125 } 126 127 def drop_set_idx(vpn: UInt, nSets: Int): UInt = { 128 require(nSets >= 1) 129 require(vpn.getWidth > log2Ceil(nSets)) 130 vpn(vpn.getWidth-1, log2Ceil(nSets)) 131 } 132 133 def drop_set_equal(vpn1: UInt, vpn2: UInt, nSets: Int): Bool = { 134 require(nSets >= 1) 135 require(vpn1.getWidth == vpn2.getWidth) 136 if (vpn1.getWidth <= log2Ceil(nSets)) { 137 true.B 138 } else { 139 drop_set_idx(vpn1, nSets) === drop_set_idx(vpn2, nSets) 140 } 141 } 142 143 def replaceWrapper(v: UInt, lruIdx: UInt): UInt = { 144 val width = v.getWidth 145 val emptyIdx = ParallelPriorityMux((0 until width).map( i => (!v(i), i.U(log2Up(width).W)))) 146 val full = Cat(v).andR 147 Mux(full, lruIdx, emptyIdx) 148 } 149 150 def replaceWrapper(v: Seq[Bool], lruIdx: UInt): UInt = { 151 replaceWrapper(VecInit(v).asUInt, lruIdx) 152 } 153 154 implicit def hptwresp_to_tlbperm(hptwResp: HptwResp): TlbPermBundle = { 155 val tp = Wire(new TlbPermBundle) 156 val ptePerm = hptwResp.entry.perm.get.asTypeOf(new PtePermBundle().cloneType) 157 tp.pf := hptwResp.gpf 158 tp.af := hptwResp.gaf 159 tp.d := ptePerm.d 160 tp.a := ptePerm.a 161 tp.g := ptePerm.g 162 tp.u := ptePerm.u 163 tp.x := ptePerm.x 164 tp.w := ptePerm.w 165 tp.r := ptePerm.r 166 tp 167 } 168 169 implicit def ptwresp_to_tlbperm(ptwResp: PtwSectorResp): TlbPermBundle = { 170 val tp = Wire(new TlbPermBundle) 171 val ptePerm = ptwResp.entry.perm.get.asTypeOf(new PtePermBundle().cloneType) 172 tp.pf := ptwResp.pf 173 tp.af := ptwResp.af 174 tp.d := ptePerm.d 175 tp.a := ptePerm.a 176 tp.g := ptePerm.g 177 tp.u := ptePerm.u 178 tp.x := ptePerm.x 179 tp.w := ptePerm.w 180 tp.r := ptePerm.r 181 tp 182 } 183} 184 185trait HasPtwConst extends HasTlbConst with MemoryOpConstants{ 186 val PtwWidth = 2 187 val sourceWidth = { if (l2tlbParams.enablePrefetch) PtwWidth + 1 else PtwWidth} 188 val prefetchID = PtwWidth 189 190 val blockBits = l2tlbParams.blockBytes * 8 191 192 val bPtwWidth = log2Up(PtwWidth) 193 val bSourceWidth = log2Up(sourceWidth) 194 // ptwl1: fully-associated 195 val PtwL1TagLen = vpnnLen + extendVpnnBits 196 197 /* +-------+----------+-------------+ 198 * | Tag | SetIdx | SectorIdx | 199 * +-------+----------+-------------+ 200 */ 201 // ptwl2: 8-way group-associated 202 val l2tlbParams.l2nWays = l2tlbParams.l2nWays 203 val PtwL2SetNum = l2tlbParams.l2nSets 204 val PtwL2SectorSize = blockBits / XLEN 205 val PtwL2IdxLen = log2Up(PtwL2SetNum * PtwL2SectorSize) 206 val PtwL2SectorIdxLen = log2Up(PtwL2SectorSize) 207 val PtwL2SetIdxLen = log2Up(PtwL2SetNum) 208 val PtwL2TagLen = vpnnLen * 2 - PtwL2IdxLen + extendVpnnBits 209 210 // ptwl3: 16-way group-associated 211 val l2tlbParams.l3nWays = l2tlbParams.l3nWays 212 val PtwL3SetNum = l2tlbParams.l3nSets 213 val PtwL3SectorSize = blockBits / XLEN 214 val PtwL3IdxLen = log2Up(PtwL3SetNum * PtwL3SectorSize) 215 val PtwL3SectorIdxLen = log2Up(PtwL3SectorSize) 216 val PtwL3SetIdxLen = log2Up(PtwL3SetNum) 217 val PtwL3TagLen = vpnnLen * 3 - PtwL3IdxLen + extendVpnnBits 218 219 // super page, including 1GB and 2MB page 220 val SPTagLen = vpnnLen * 2 + extendVpnnBits 221 222 // miss queue 223 val MissQueueSize = l2tlbParams.ifilterSize + l2tlbParams.dfilterSize 224 val MemReqWidth = l2tlbParams.llptwsize + 1 + 1 225 val HptwReqId = l2tlbParams.llptwsize + 1 226 val FsmReqID = l2tlbParams.llptwsize 227 val bMemID = log2Up(MemReqWidth) 228 229 def genPtwL2Idx(vpn: UInt) = { 230 (vpn(vpnLen - 1, vpnnLen))(PtwL2IdxLen - 1, 0) 231 } 232 233 def genPtwL2SectorIdx(vpn: UInt) = { 234 genPtwL2Idx(vpn)(PtwL2SectorIdxLen - 1, 0) 235 } 236 237 def genPtwL2SetIdx(vpn: UInt) = { 238 genPtwL2Idx(vpn)(PtwL2SetIdxLen + PtwL2SectorIdxLen - 1, PtwL2SectorIdxLen) 239 } 240 241 def genPtwL3Idx(vpn: UInt) = { 242 vpn(PtwL3IdxLen - 1, 0) 243 } 244 245 def genPtwL3SectorIdx(vpn: UInt) = { 246 genPtwL3Idx(vpn)(PtwL3SectorIdxLen - 1, 0) 247 } 248 249 def dropL3SectorBits(vpn: UInt) = { 250 vpn(vpn.getWidth-1, PtwL3SectorIdxLen) 251 } 252 253 def genPtwL3SetIdx(vpn: UInt) = { 254 genPtwL3Idx(vpn)(PtwL3SetIdxLen + PtwL3SectorIdxLen - 1, PtwL3SectorIdxLen) 255 } 256 257 def MakeAddr(ppn: UInt, off: UInt) = { 258 require(off.getWidth == 9) 259 Cat(ppn, off, 0.U(log2Up(XLEN/8).W))(PAddrBits-1, 0) 260 } 261 262 def MakeGPAddr(ppn: UInt, off: UInt) = { 263 require(off.getWidth == 9 || off.getWidth == 11) 264 (Cat(ppn, 0.U(offLen.W)) + Cat(off, 0.U(log2Up(XLEN / 8).W)))(GPAddrBits - 1, 0) 265 } 266 267 def getVpnn(vpn: UInt, idx: Int): UInt = { 268 vpn(vpnnLen*(idx+1)-1, vpnnLen*idx) 269 } 270 271 def getVpnn(vpn: UInt, idx: UInt): UInt = { 272 Mux(idx === 0.U, vpn(vpnnLen - 1, 0), Mux(idx === 1.U, vpn(vpnnLen * 2 - 1, vpnnLen), vpn(vpnnLen * 3 - 1, vpnnLen * 2))) 273 } 274 275 def getGVpnn(vpn: UInt, idx: UInt): UInt = { 276 Mux(idx === 0.U, vpn(vpnnLen - 1, 0), Mux(idx === 1.U, vpn(vpnnLen * 2 - 1, vpnnLen), vpn(vpnnLen * 3 + 1, vpnnLen * 2))) 277 } 278 279 def getVpnClip(vpn: UInt, level: Int) = { 280 // level 0 /* vpnn2 */ 281 // level 1 /* vpnn2 * vpnn1 */ 282 // level 2 /* vpnn2 * vpnn1 * vpnn0*/ 283 vpn(vpnLen - 1, (2 - level) * vpnnLen) 284 } 285 286 def get_next_line(vpn: UInt) = { 287 Cat(dropL3SectorBits(vpn) + 1.U, 0.U(PtwL3SectorIdxLen.W)) 288 } 289 290 def same_l2entry(vpn1: UInt, vpn2: UInt) = { 291 vpn1(vpnLen-1, vpnnLen) === vpn2(vpnLen-1, vpnnLen) 292 } 293 294 def from_pre(source: UInt) = { 295 (source === prefetchID.U) 296 } 297 298 def sel_data(data: UInt, index: UInt): UInt = { 299 val inner_data = data.asTypeOf(Vec(data.getWidth / XLEN, UInt(XLEN.W))) 300 inner_data(index) 301 } 302 303 // vpn1 and vpn2 is at same cacheline 304 def dup(vpn1: UInt, vpn2: UInt): Bool = { 305 dropL3SectorBits(vpn1) === dropL3SectorBits(vpn2) 306 } 307 308 309 def printVec[T <: Data](x: Seq[T]): Printable = { 310 (0 until x.length).map(i => p"(${i.U})${x(i)} ").reduce(_+_) 311 } 312} 313