1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.cache.mmu 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import xiangshan._ 23import xiangshan.cache.{HasDCacheParameters, MemoryOpConstants} 24import utils._ 25import utility._ 26import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 27import freechips.rocketchip.tilelink._ 28 29 30case class TLBParameters 31( 32 name: String = "none", 33 fetchi: Boolean = false, // TODO: remove it 34 fenceDelay: Int = 2, 35 useDmode: Boolean = true, 36 NSets: Int = 1, 37 NWays: Int = 2, 38 Replacer: Option[String] = Some("plru"), 39 Associative: String = "fa", // must be fa 40 outReplace: Boolean = false, 41 partialStaticPMP: Boolean = false, // partial static pmp result stored in entries 42 outsideRecvFlush: Boolean = false, // if outside moudle waiting for tlb recv flush pipe 43 saveLevel: Boolean = false 44) 45 46case class L2TLBParameters 47( 48 name: String = "l2tlb", 49 // l1 50 l1Size: Int = 16, 51 l1Associative: String = "fa", 52 l1Replacer: Option[String] = Some("plru"), 53 // l2 54 l2nSets: Int = 8, 55 l2nWays: Int = 4, 56 l2Replacer: Option[String] = Some("setplru"), 57 // l3 58 l3nSets: Int = 32, 59 l3nWays: Int = 8, 60 l3Replacer: Option[String] = Some("setplru"), 61 // sp 62 spSize: Int = 16, 63 spReplacer: Option[String] = Some("plru"), 64 // filter 65 ifilterSize: Int = 8, 66 dfilterSize: Int = 32, 67 // miss queue, add more entries than 'must require' 68 // 0 for easier bug trigger, please set as big as u can, 8 maybe 69 missqueueExtendSize: Int = 0, 70 // llptw 71 llptwsize: Int = 6, 72 // way size 73 blockBytes: Int = 64, 74 // prefetch 75 enablePrefetch: Boolean = true, 76 // ecc 77 ecc: Option[String] = Some("secded") 78) 79 80trait HasTlbConst extends HasXSParameter { 81 val Level = 3 82 83 val offLen = 12 84 val ppnLen = PAddrBits - offLen 85 val vpnnLen = 9 86 val extendVpnnBits = if (HasHExtension) 2 else 0 87 val vpnLen = VAddrBits - offLen // when opening H extention, vpnlen broaden two bits 88 val flagLen = 8 89 val pteResLen = XLEN - 44 - 2 - flagLen 90 val ppnHignLen = 44 - ppnLen 91 92 val tlbcontiguous = 8 93 val sectortlbwidth = log2Up(tlbcontiguous) 94 val sectorppnLen = ppnLen - sectortlbwidth 95 val sectorvpnLen = vpnLen - sectortlbwidth 96 97 val loadfiltersize = 16 98 val storefiltersize = 8 99 val prefetchfiltersize = 8 100 val sramSinglePort = true 101 102 val timeOutThreshold = 10000 103 104 def noS2xlate = "b00".U 105 def allStage = "b11".U 106 def onlyStage1 = "b01".U 107 def onlyStage2 = "b10".U 108 109 def get_pn(addr: UInt) = { 110 require(addr.getWidth > offLen) 111 addr(addr.getWidth-1, offLen) 112 } 113 def get_off(addr: UInt) = { 114 require(addr.getWidth > offLen) 115 addr(offLen-1, 0) 116 } 117 118 def get_set_idx(vpn: UInt, nSets: Int): UInt = { 119 require(nSets >= 1) 120 vpn(log2Up(nSets)-1, 0) 121 } 122 123 def drop_set_idx(vpn: UInt, nSets: Int): UInt = { 124 require(nSets >= 1) 125 require(vpn.getWidth > log2Ceil(nSets)) 126 vpn(vpn.getWidth-1, log2Ceil(nSets)) 127 } 128 129 def drop_set_equal(vpn1: UInt, vpn2: UInt, nSets: Int): Bool = { 130 require(nSets >= 1) 131 require(vpn1.getWidth == vpn2.getWidth) 132 if (vpn1.getWidth <= log2Ceil(nSets)) { 133 true.B 134 } else { 135 drop_set_idx(vpn1, nSets) === drop_set_idx(vpn2, nSets) 136 } 137 } 138 139 def replaceWrapper(v: UInt, lruIdx: UInt): UInt = { 140 val width = v.getWidth 141 val emptyIdx = ParallelPriorityMux((0 until width).map( i => (!v(i), i.U(log2Up(width).W)))) 142 val full = Cat(v).andR 143 Mux(full, lruIdx, emptyIdx) 144 } 145 146 def replaceWrapper(v: Seq[Bool], lruIdx: UInt): UInt = { 147 replaceWrapper(VecInit(v).asUInt, lruIdx) 148 } 149 150 implicit def hptwresp_to_tlbperm(hptwResp: HptwResp): TlbPermBundle = { 151 val tp = Wire(new TlbPermBundle) 152 val ptePerm = hptwResp.entry.perm.get.asTypeOf(new PtePermBundle().cloneType) 153 tp.pf := hptwResp.gpf 154 tp.af := hptwResp.gaf 155 tp.d := ptePerm.d 156 tp.a := ptePerm.a 157 tp.g := ptePerm.g 158 tp.u := ptePerm.u 159 tp.x := ptePerm.x 160 tp.w := ptePerm.w 161 tp.r := ptePerm.r 162 tp 163 } 164 165 implicit def ptwresp_to_tlbperm(ptwResp: PtwSectorResp): TlbPermBundle = { 166 val tp = Wire(new TlbPermBundle) 167 val ptePerm = ptwResp.entry.perm.get.asTypeOf(new PtePermBundle().cloneType) 168 tp.pf := ptwResp.pf 169 tp.af := ptwResp.af 170 tp.d := ptePerm.d 171 tp.a := ptePerm.a 172 tp.g := ptePerm.g 173 tp.u := ptePerm.u 174 tp.x := ptePerm.x 175 tp.w := ptePerm.w 176 tp.r := ptePerm.r 177 tp 178 } 179} 180 181trait HasPtwConst extends HasTlbConst with MemoryOpConstants{ 182 val PtwWidth = 2 183 val sourceWidth = { if (l2tlbParams.enablePrefetch) PtwWidth + 1 else PtwWidth} 184 val prefetchID = PtwWidth 185 186 val blockBits = l2tlbParams.blockBytes * 8 187 188 val bPtwWidth = log2Up(PtwWidth) 189 val bSourceWidth = log2Up(sourceWidth) 190 // ptwl1: fully-associated 191 val PtwL1TagLen = vpnnLen + extendVpnnBits 192 193 /* +-------+----------+-------------+ 194 * | Tag | SetIdx | SectorIdx | 195 * +-------+----------+-------------+ 196 */ 197 // ptwl2: 8-way group-associated 198 val l2tlbParams.l2nWays = l2tlbParams.l2nWays 199 val PtwL2SetNum = l2tlbParams.l2nSets 200 val PtwL2SectorSize = blockBits / XLEN 201 val PtwL2IdxLen = log2Up(PtwL2SetNum * PtwL2SectorSize) 202 val PtwL2SectorIdxLen = log2Up(PtwL2SectorSize) 203 val PtwL2SetIdxLen = log2Up(PtwL2SetNum) 204 val PtwL2TagLen = vpnnLen * 2 - PtwL2IdxLen + extendVpnnBits 205 206 // ptwl3: 16-way group-associated 207 val l2tlbParams.l3nWays = l2tlbParams.l3nWays 208 val PtwL3SetNum = l2tlbParams.l3nSets 209 val PtwL3SectorSize = blockBits / XLEN 210 val PtwL3IdxLen = log2Up(PtwL3SetNum * PtwL3SectorSize) 211 val PtwL3SectorIdxLen = log2Up(PtwL3SectorSize) 212 val PtwL3SetIdxLen = log2Up(PtwL3SetNum) 213 val PtwL3TagLen = vpnnLen * 3 - PtwL3IdxLen + extendVpnnBits 214 215 // super page, including 1GB and 2MB page 216 val SPTagLen = vpnnLen * 2 + extendVpnnBits 217 218 // miss queue 219 val MissQueueSize = l2tlbParams.ifilterSize + l2tlbParams.dfilterSize 220 val MemReqWidth = l2tlbParams.llptwsize + 1 + 1 221 val HptwReqId = l2tlbParams.llptwsize + 1 222 val FsmReqID = l2tlbParams.llptwsize 223 val bMemID = log2Up(MemReqWidth) 224 225 def genPtwL2Idx(vpn: UInt) = { 226 (vpn(vpnLen - 1, vpnnLen))(PtwL2IdxLen - 1, 0) 227 } 228 229 def genPtwL2SectorIdx(vpn: UInt) = { 230 genPtwL2Idx(vpn)(PtwL2SectorIdxLen - 1, 0) 231 } 232 233 def genPtwL2SetIdx(vpn: UInt) = { 234 genPtwL2Idx(vpn)(PtwL2SetIdxLen + PtwL2SectorIdxLen - 1, PtwL2SectorIdxLen) 235 } 236 237 def genPtwL3Idx(vpn: UInt) = { 238 vpn(PtwL3IdxLen - 1, 0) 239 } 240 241 def genPtwL3SectorIdx(vpn: UInt) = { 242 genPtwL3Idx(vpn)(PtwL3SectorIdxLen - 1, 0) 243 } 244 245 def dropL3SectorBits(vpn: UInt) = { 246 vpn(vpn.getWidth-1, PtwL3SectorIdxLen) 247 } 248 249 def genPtwL3SetIdx(vpn: UInt) = { 250 genPtwL3Idx(vpn)(PtwL3SetIdxLen + PtwL3SectorIdxLen - 1, PtwL3SectorIdxLen) 251 } 252 253 def MakeAddr(ppn: UInt, off: UInt) = { 254 require(off.getWidth == 9) 255 Cat(ppn, off, 0.U(log2Up(XLEN/8).W))(PAddrBits-1, 0) 256 } 257 258 def MakeGAddr(ppn: UInt, off: UInt) = { 259 require(off.getWidth == 9 || off.getWidth == 11) 260 (Cat(ppn, 0.U(offLen.W)) + Cat(off, 0.U(log2Up(XLEN / 8).W)))(GPAddrBits - 1, 0) 261 } 262 263 def getVpnn(vpn: UInt, idx: Int): UInt = { 264 vpn(vpnnLen*(idx+1)-1, vpnnLen*idx) 265 } 266 267 def getVpnn(vpn: UInt, idx: UInt): UInt = { 268 Mux(idx === 0.U, vpn(vpnnLen - 1, 0), Mux(idx === 1.U, vpn(vpnnLen * 2 - 1, vpnnLen), vpn(vpnnLen * 3 - 1, vpnnLen * 2))) 269 } 270 271 def getGVpnn(vpn: UInt, idx: UInt): UInt = { 272 Mux(idx === 0.U, vpn(vpnnLen - 1, 0), Mux(idx === 1.U, vpn(vpnnLen * 2 - 1, vpnnLen), vpn(vpnnLen * 3 + 1, vpnnLen * 2))) 273 } 274 275 def getVpnClip(vpn: UInt, level: Int) = { 276 // level 0 /* vpnn2 */ 277 // level 1 /* vpnn2 * vpnn1 */ 278 // level 2 /* vpnn2 * vpnn1 * vpnn0*/ 279 vpn(vpnLen - 1, (2 - level) * vpnnLen) 280 } 281 282 def get_next_line(vpn: UInt) = { 283 Cat(dropL3SectorBits(vpn) + 1.U, 0.U(PtwL3SectorIdxLen.W)) 284 } 285 286 def same_l2entry(vpn1: UInt, vpn2: UInt) = { 287 vpn1(vpnLen-1, vpnnLen) === vpn2(vpnLen-1, vpnnLen) 288 } 289 290 def from_pre(source: UInt) = { 291 (source === prefetchID.U) 292 } 293 294 def sel_data(data: UInt, index: UInt): UInt = { 295 val inner_data = data.asTypeOf(Vec(data.getWidth / XLEN, UInt(XLEN.W))) 296 inner_data(index) 297 } 298 299 // vpn1 and vpn2 is at same cacheline 300 def dup(vpn1: UInt, vpn2: UInt): Bool = { 301 dropL3SectorBits(vpn1) === dropL3SectorBits(vpn2) 302 } 303 304 305 def printVec[T <: Data](x: Seq[T]): Printable = { 306 (0 until x.length).map(i => p"(${i.U})${x(i)} ").reduce(_+_) 307 } 308} 309