1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.decode 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.rocket.DecodeLogic 23import freechips.rocketchip.rocket.Instructions._ 24import xiangshan.backend.decode.isa.bitfield.XSInstBitFields 25import xiangshan.backend.fu.fpu.FPU 26import xiangshan.{FPUCtrlSignals, XSModule} 27 28class FPDecoder(implicit p: Parameters) extends XSModule{ 29 val io = IO(new Bundle() { 30 val instr = Input(UInt(32.W)) 31 val fpCtrl = Output(new FPUCtrlSignals) 32 }) 33 34 private val inst: XSInstBitFields = io.instr.asTypeOf(new XSInstBitFields) 35 36 def X = BitPat("b?") 37 def N = BitPat("b0") 38 def Y = BitPat("b1") 39 val s = BitPat(FPU.S) 40 val d = BitPat(FPU.D) 41 val i = BitPat(FPU.D) 42 43 val default = List(X,X,X,N,N,N,X,X,X) 44 45 // isAddSub tagIn tagOut fromInt wflags fpWen div sqrt fcvt 46 val single: Array[(BitPat, List[BitPat])] = Array( 47 // IntToFP 48 FMV_W_X -> List(N,i,s,Y,N,Y,N,N,N), 49 FCVT_S_W -> List(N,i,s,Y,Y,Y,N,N,Y), 50 FCVT_S_WU-> List(N,i,s,Y,Y,Y,N,N,Y), 51 FCVT_S_L -> List(N,i,s,Y,Y,Y,N,N,Y), 52 FCVT_S_LU-> List(N,i,s,Y,Y,Y,N,N,Y), 53 // FPToInt 54 FMV_X_W -> List(N,d,i,N,N,N,N,N,N), // dont box result of fmv.fp.int 55 FCLASS_S -> List(N,s,i,N,N,N,N,N,N), 56 FCVT_W_S -> List(N,s,i,N,Y,N,N,N,Y), 57 FCVT_WU_S-> List(N,s,i,N,Y,N,N,N,Y), 58 FCVT_L_S -> List(N,s,i,N,Y,N,N,N,Y), 59 FCVT_LU_S-> List(N,s,i,N,Y,N,N,N,Y), 60 FEQ_S -> List(N,s,i,N,Y,N,N,N,N), 61 FLT_S -> List(N,s,i,N,Y,N,N,N,N), 62 FLE_S -> List(N,s,i,N,Y,N,N,N,N), 63 // FPToFP 64 FSGNJ_S -> List(N,s,s,N,N,Y,N,N,N), 65 FSGNJN_S -> List(N,s,s,N,N,Y,N,N,N), 66 FSGNJX_S -> List(N,s,s,N,N,Y,N,N,N), 67 FMIN_S -> List(N,s,s,N,Y,Y,N,N,N), 68 FMAX_S -> List(N,s,s,N,Y,Y,N,N,N), 69 FADD_S -> List(Y,s,s,N,Y,Y,N,N,N), 70 FSUB_S -> List(Y,s,s,N,Y,Y,N,N,N), 71 FMUL_S -> List(N,s,s,N,Y,Y,N,N,N), 72 FMADD_S -> List(N,s,s,N,Y,Y,N,N,N), 73 FMSUB_S -> List(N,s,s,N,Y,Y,N,N,N), 74 FNMADD_S -> List(N,s,s,N,Y,Y,N,N,N), 75 FNMSUB_S -> List(N,s,s,N,Y,Y,N,N,N), 76 FDIV_S -> List(N,s,s,N,Y,Y,Y,N,N), 77 FSQRT_S -> List(N,s,s,N,Y,Y,N,Y,N) 78 ) 79 80 81 // isAddSub tagIn tagOut fromInt wflags fpWen div sqrt fcvt 82 val double: Array[(BitPat, List[BitPat])] = Array( 83 FMV_D_X -> List(N,i,d,Y,N,Y,N,N,N), 84 FCVT_D_W -> List(N,i,d,Y,Y,Y,N,N,Y), 85 FCVT_D_WU-> List(N,i,d,Y,Y,Y,N,N,Y), 86 FCVT_D_L -> List(N,i,d,Y,Y,Y,N,N,Y), 87 FCVT_D_LU-> List(N,i,d,Y,Y,Y,N,N,Y), 88 FMV_X_D -> List(N,d,i,N,N,N,N,N,N), 89 FCLASS_D -> List(N,d,i,N,N,N,N,N,N), 90 FCVT_W_D -> List(N,d,i,N,Y,N,N,N,Y), 91 FCVT_WU_D-> List(N,d,i,N,Y,N,N,N,Y), 92 FCVT_L_D -> List(N,d,i,N,Y,N,N,N,Y), 93 FCVT_LU_D-> List(N,d,i,N,Y,N,N,N,Y), 94 FCVT_S_D -> List(N,d,s,N,Y,Y,N,N,Y), 95 FCVT_D_S -> List(N,s,d,N,Y,Y,N,N,Y), 96 FEQ_D -> List(N,d,i,N,Y,N,N,N,N), 97 FLT_D -> List(N,d,i,N,Y,N,N,N,N), 98 FLE_D -> List(N,d,i,N,Y,N,N,N,N), 99 FSGNJ_D -> List(N,d,d,N,N,Y,N,N,N), 100 FSGNJN_D -> List(N,d,d,N,N,Y,N,N,N), 101 FSGNJX_D -> List(N,d,d,N,N,Y,N,N,N), 102 FMIN_D -> List(N,d,d,N,Y,Y,N,N,N), 103 FMAX_D -> List(N,d,d,N,Y,Y,N,N,N), 104 FADD_D -> List(Y,d,d,N,Y,Y,N,N,N), 105 FSUB_D -> List(Y,d,d,N,Y,Y,N,N,N), 106 FMUL_D -> List(N,d,d,N,Y,Y,N,N,N), 107 FMADD_D -> List(N,d,d,N,Y,Y,N,N,N), 108 FMSUB_D -> List(N,d,d,N,Y,Y,N,N,N), 109 FNMADD_D -> List(N,d,d,N,Y,Y,N,N,N), 110 FNMSUB_D -> List(N,d,d,N,Y,Y,N,N,N), 111 FDIV_D -> List(N,d,d,N,Y,Y,Y,N,N), 112 FSQRT_D -> List(N,d,d,N,Y,Y,N,Y,N) 113 ) 114 115 val table = single ++ double 116 117 val decoder = DecodeLogic(io.instr, default, table) 118 119 val ctrl = io.fpCtrl 120 val sigs = Seq( 121 ctrl.isAddSub, ctrl.typeTagIn, ctrl.typeTagOut, 122 ctrl.fromInt, ctrl.wflags, ctrl.fpWen, 123 ctrl.div, ctrl.sqrt, ctrl.fcvt 124 ) 125 sigs.zip(decoder).foreach({case (s, d) => s := d}) 126 ctrl.typ := inst.TYP 127 ctrl.fmt := inst.FMT 128 ctrl.rm := inst.RM 129 130 val fmaTable: Array[(BitPat, List[BitPat])] = Array( 131 FADD_S -> List(BitPat("b00"),N), 132 FADD_D -> List(BitPat("b00"),N), 133 FSUB_S -> List(BitPat("b01"),N), 134 FSUB_D -> List(BitPat("b01"),N), 135 FMUL_S -> List(BitPat("b00"),N), 136 FMUL_D -> List(BitPat("b00"),N), 137 FMADD_S -> List(BitPat("b00"),Y), 138 FMADD_D -> List(BitPat("b00"),Y), 139 FMSUB_S -> List(BitPat("b01"),Y), 140 FMSUB_D -> List(BitPat("b01"),Y), 141 FNMADD_S-> List(BitPat("b11"),Y), 142 FNMADD_D-> List(BitPat("b11"),Y), 143 FNMSUB_S-> List(BitPat("b10"),Y), 144 FNMSUB_D-> List(BitPat("b10"),Y) 145 ) 146 val fmaDefault = List(BitPat("b??"), N) 147 Seq(ctrl.fmaCmd, ctrl.ren3).zip( 148 DecodeLogic(io.instr, fmaDefault, fmaTable) 149 ).foreach({ 150 case (s, d) => s := d 151 }) 152} 153