fix(fpDecoder): fix bug of fmt

fix(decode): scala fp fu's fmt use fpuCtrl instead of vsew

busytable: support eliminate old vd when read vl's state

fix(FPDecoder):fix fmaTable

fix some bug

feat(zvfh,zfh): add F16 support

feat(riscv64): Support RISC-V Zfa extension

* Support fli.{h.s.d}, fminm.{h.s.d}, fmaxm.{h.s.d}
* Support fround.{h.s.d}, froundnx.{h.s.d}, fcvtmod.w.d
* Support fleq.{h.s.d}, fltq.{h.s.d}

zfhmin:add zfhmin extensions

*decode unit adds decoding of zfhmin extension related instructions
*Re exemplified the functional units for scalar fpcvt

Merge branch 'master' into vlsu-merge-master-0504

Decode: correctly specify fp inst's src num

rv64v: fix some corner case when reduction intsurctinos depend on oldvd

rv64v: add ignore oldvd judgement in issue queue
1. when the instruction depend on old vd, we cannot set the srctype to imm
2. when vl = 0, we cannot set the srctype to imm because the vd keep the ol

rv64v: add ignore oldvd judgement in issue queue
1. when the instruction depend on old vd, we cannot set the srctype to imm
2. when vl = 0, we cannot set the srctype to imm because the vd keep the old value
3. when vl = vlmax, we can set srctype to imm when vta is not se

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float: use VCVT module for all fcvt instructions
Co-authored-by: chengguanghui <[email protected]>

float: use VCVT module for all fcvt instructions
Co-authored-by: chengguanghui <[email protected]>

rv64v: add f2v to remove all fs1 duplicate logic (#2613)

* rv64v: add f2v to remove all fs1 duplicate logic

* rv64v: use IntFPToVec module for i2v and f2v

rv64v: add veew in VPUCtrlSignals (#2434)

rv64v: support all opivi instructions use i2v

Merge upstream/master into tmp-backend-merge-master

Bump rocket-chip (#2353)

rv64v: fix vmask instructions' tail elements
*pass: vmand.mm, vmnand.mm, vmandn.mm, vmxor.mm, vmor.mm, vmnor.mm, vmorn.mm, vmxnor.mm

exu: vector float units(vfalu,vfma,vfdivsqrt) execute scalar float instructions

mod: refactor the code of encoding

fix for chipsalliance/rocket-chip#2967 (#1562)

* fix for chipsalliance/rocket-chip#2967

* decode: fix width of BitPat(?) in decode logic

Co-authored-by: Yinan Xu <[email protected]>

fudian: The new floating-point lib to replace hardfloat (#975)

* Add submodule 'fudian'

* IntToFP: use fudian

* FMA: use fudian.CMA

* FPToInt: remove recode format

misc: update PCL information (#899)

XiangShan is jointly released by ICT and PCL.

Add MulanPSL-2.0 License (#824)

In this commit, we add License for XiangShan project.