1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.decode 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.rocket.DecodeLogic 23import freechips.rocketchip.rocket.Instructions._ 24import xiangshan.backend.decode.isa.bitfield.XSInstBitFields 25import xiangshan.backend.fu.fpu.FPU 26import xiangshan.backend.fu.vector.Bundles.{VSew, VLmul} 27import xiangshan.backend.Bundles.VPUCtrlSignals 28import xiangshan.{FPUCtrlSignals, XSModule} 29 30class FPToVecDecoder(implicit p: Parameters) extends XSModule { 31 val io = IO(new Bundle() { 32 val instr = Input(UInt(32.W)) 33 val vpuCtrl = Output(new VPUCtrlSignals) 34 }) 35 36 val inst = io.instr.asTypeOf(new XSInstBitFields) 37 val fpToVecInsts = Seq( 38 FADD_S, FSUB_S, FADD_D, FSUB_D, 39 FEQ_S, FLT_S, FLE_S, FEQ_D, FLT_D, FLE_D, 40 FMIN_S, FMAX_S, FMIN_D, FMAX_D, 41 FMUL_S, FMUL_D, 42 FDIV_S, FDIV_D, FSQRT_S, FSQRT_D, 43 FMADD_S, FMSUB_S, FNMADD_S, FNMSUB_S, FMADD_D, FMSUB_D, FNMADD_D, FNMSUB_D, 44 FCLASS_S, FCLASS_D, FSGNJ_S, FSGNJ_D, FSGNJX_S, FSGNJX_D, FSGNJN_S, FSGNJN_D, 45 46 // scalar cvt inst 47 FCVT_W_S, FCVT_WU_S, FCVT_L_S, FCVT_LU_S, 48 FCVT_W_D, FCVT_WU_D, FCVT_L_D, FCVT_LU_D, FCVT_S_D, FCVT_D_S, 49 FMV_X_W, FMV_X_D, 50 ) 51 val isFpToVecInst = fpToVecInsts.map(io.instr === _).reduce(_ || _) 52 val isFP32Instrs = Seq( 53 FADD_S, FSUB_S, FEQ_S, FLT_S, FLE_S, FMIN_S, FMAX_S, 54 FMUL_S, FDIV_S, FSQRT_S, 55 FMADD_S, FMSUB_S, FNMADD_S, FNMSUB_S, 56 FCLASS_S, FSGNJ_S, FSGNJX_S, FSGNJN_S, 57 ) 58 val isFP32Instr = isFP32Instrs.map(io.instr === _).reduce(_ || _) 59 val isFP64Instrs = Seq( 60 FADD_D, FSUB_D, FEQ_D, FLT_D, FLE_D, FMIN_D, FMAX_D, 61 FMUL_D, FDIV_D, FSQRT_D, 62 FMADD_D, FMSUB_D, FNMADD_D, FNMSUB_D, 63 FCLASS_D, FSGNJ_D, FSGNJX_D, FSGNJN_D, 64 ) 65 val isFP64Instr = isFP64Instrs.map(io.instr === _).reduce(_ || _) 66 // scalar cvt inst 67 val isSew2Cvts = Seq( 68 FCVT_W_S, FCVT_WU_S, FCVT_L_S, FCVT_LU_S, 69 FCVT_W_D, FCVT_WU_D, FCVT_S_D, FCVT_D_S, 70 FMV_X_W, 71 ) 72 val isSew2Cvt = isSew2Cvts.map(io.instr === _).reduce(_ || _) 73 val isLmulMf4Cvts = Seq( 74 FCVT_W_S, FCVT_WU_S, 75 FMV_X_W, 76 ) 77 val isLmulMf4Cvt = isLmulMf4Cvts.map(io.instr === _).reduce(_ || _) 78 val needReverseInsts = fpToVecInsts 79 val needReverseInst = needReverseInsts.map(_ === inst.ALL).reduce(_ || _) 80 io.vpuCtrl := 0.U.asTypeOf(io.vpuCtrl) 81 io.vpuCtrl.fpu.isFpToVecInst := isFpToVecInst 82 io.vpuCtrl.fpu.isFP32Instr := isFP32Instr 83 io.vpuCtrl.fpu.isFP64Instr := isFP64Instr 84 io.vpuCtrl.vill := false.B 85 io.vpuCtrl.vma := true.B 86 io.vpuCtrl.vta := true.B 87 io.vpuCtrl.vsew := Mux(isFP32Instr || isSew2Cvt, VSew.e32, VSew.e64) 88 io.vpuCtrl.vlmul := Mux(isFP32Instr || isLmulMf4Cvt, VLmul.mf4, VLmul.mf2) 89 io.vpuCtrl.vm := inst.VM 90 io.vpuCtrl.nf := inst.NF 91 io.vpuCtrl.veew := inst.WIDTH 92 io.vpuCtrl.isReverse := needReverseInst 93 io.vpuCtrl.isExt := false.B 94 io.vpuCtrl.isNarrow := false.B 95 io.vpuCtrl.isDstMask := false.B 96 io.vpuCtrl.isOpMask := false.B 97} 98 99 100class FPDecoder(implicit p: Parameters) extends XSModule{ 101 val io = IO(new Bundle() { 102 val instr = Input(UInt(32.W)) 103 val fpCtrl = Output(new FPUCtrlSignals) 104 }) 105 106 private val inst: XSInstBitFields = io.instr.asTypeOf(new XSInstBitFields) 107 108 def X = BitPat("b?") 109 def N = BitPat("b0") 110 def Y = BitPat("b1") 111 val s = BitPat(FPU.S) 112 val d = BitPat(FPU.D) 113 val i = BitPat(FPU.D) 114 115 val default = List(X,X,X,N,N,N,X,X,X) 116 117 // isAddSub tagIn tagOut fromInt wflags fpWen div sqrt fcvt 118 val single: Array[(BitPat, List[BitPat])] = Array( 119 // IntToFP 120 FMV_W_X -> List(N,i,s,Y,N,Y,N,N,N), 121 FCVT_S_W -> List(N,i,s,Y,Y,Y,N,N,Y), 122 FCVT_S_WU-> List(N,i,s,Y,Y,Y,N,N,Y), 123 FCVT_S_L -> List(N,i,s,Y,Y,Y,N,N,Y), 124 FCVT_S_LU-> List(N,i,s,Y,Y,Y,N,N,Y), 125 // FPToInt 126 FMV_X_W -> List(N,d,i,N,N,N,N,N,N), // dont box result of fmv.fp.int 127 FCLASS_S -> List(N,s,i,N,N,N,N,N,N), 128 FCVT_W_S -> List(N,s,i,N,Y,N,N,N,Y), 129 FCVT_WU_S-> List(N,s,i,N,Y,N,N,N,Y), 130 FCVT_L_S -> List(N,s,i,N,Y,N,N,N,Y), 131 FCVT_LU_S-> List(N,s,i,N,Y,N,N,N,Y), 132 FEQ_S -> List(N,s,i,N,Y,N,N,N,N), 133 FLT_S -> List(N,s,i,N,Y,N,N,N,N), 134 FLE_S -> List(N,s,i,N,Y,N,N,N,N), 135 // FPToFP 136 FSGNJ_S -> List(N,s,s,N,N,Y,N,N,N), 137 FSGNJN_S -> List(N,s,s,N,N,Y,N,N,N), 138 FSGNJX_S -> List(N,s,s,N,N,Y,N,N,N), 139 FMIN_S -> List(N,s,s,N,Y,Y,N,N,N), 140 FMAX_S -> List(N,s,s,N,Y,Y,N,N,N), 141 FADD_S -> List(Y,s,s,N,Y,Y,N,N,N), 142 FSUB_S -> List(Y,s,s,N,Y,Y,N,N,N), 143 FMUL_S -> List(N,s,s,N,Y,Y,N,N,N), 144 FMADD_S -> List(N,s,s,N,Y,Y,N,N,N), 145 FMSUB_S -> List(N,s,s,N,Y,Y,N,N,N), 146 FNMADD_S -> List(N,s,s,N,Y,Y,N,N,N), 147 FNMSUB_S -> List(N,s,s,N,Y,Y,N,N,N), 148 FDIV_S -> List(N,s,s,N,Y,Y,Y,N,N), 149 FSQRT_S -> List(N,s,s,N,Y,Y,N,Y,N) 150 ) 151 152 153 // isAddSub tagIn tagOut fromInt wflags fpWen div sqrt fcvt 154 val double: Array[(BitPat, List[BitPat])] = Array( 155 FMV_D_X -> List(N,i,d,Y,N,Y,N,N,N), 156 FCVT_D_W -> List(N,i,d,Y,Y,Y,N,N,Y), 157 FCVT_D_WU-> List(N,i,d,Y,Y,Y,N,N,Y), 158 FCVT_D_L -> List(N,i,d,Y,Y,Y,N,N,Y), 159 FCVT_D_LU-> List(N,i,d,Y,Y,Y,N,N,Y), 160 FMV_X_D -> List(N,d,i,N,N,N,N,N,N), 161 FCLASS_D -> List(N,d,i,N,N,N,N,N,N), 162 FCVT_W_D -> List(N,d,i,N,Y,N,N,N,Y), 163 FCVT_WU_D-> List(N,d,i,N,Y,N,N,N,Y), 164 FCVT_L_D -> List(N,d,i,N,Y,N,N,N,Y), 165 FCVT_LU_D-> List(N,d,i,N,Y,N,N,N,Y), 166 FCVT_S_D -> List(N,d,s,N,Y,Y,N,N,Y), 167 FCVT_D_S -> List(N,s,d,N,Y,Y,N,N,Y), 168 FEQ_D -> List(N,d,i,N,Y,N,N,N,N), 169 FLT_D -> List(N,d,i,N,Y,N,N,N,N), 170 FLE_D -> List(N,d,i,N,Y,N,N,N,N), 171 FSGNJ_D -> List(N,d,d,N,N,Y,N,N,N), 172 FSGNJN_D -> List(N,d,d,N,N,Y,N,N,N), 173 FSGNJX_D -> List(N,d,d,N,N,Y,N,N,N), 174 FMIN_D -> List(N,d,d,N,Y,Y,N,N,N), 175 FMAX_D -> List(N,d,d,N,Y,Y,N,N,N), 176 FADD_D -> List(Y,d,d,N,Y,Y,N,N,N), 177 FSUB_D -> List(Y,d,d,N,Y,Y,N,N,N), 178 FMUL_D -> List(N,d,d,N,Y,Y,N,N,N), 179 FMADD_D -> List(N,d,d,N,Y,Y,N,N,N), 180 FMSUB_D -> List(N,d,d,N,Y,Y,N,N,N), 181 FNMADD_D -> List(N,d,d,N,Y,Y,N,N,N), 182 FNMSUB_D -> List(N,d,d,N,Y,Y,N,N,N), 183 FDIV_D -> List(N,d,d,N,Y,Y,Y,N,N), 184 FSQRT_D -> List(N,d,d,N,Y,Y,N,Y,N) 185 ) 186 187 val table = single ++ double 188 189 val decoder = DecodeLogic(io.instr, default, table) 190 191 val ctrl = io.fpCtrl 192 val sigs = Seq( 193 ctrl.isAddSub, ctrl.typeTagIn, ctrl.typeTagOut, 194 ctrl.fromInt, ctrl.wflags, ctrl.fpWen, 195 ctrl.div, ctrl.sqrt, ctrl.fcvt 196 ) 197 sigs.zip(decoder).foreach({case (s, d) => s := d}) 198 ctrl.typ := inst.TYP 199 ctrl.fmt := inst.FMT 200 ctrl.rm := inst.RM 201 202 val fmaTable: Array[(BitPat, List[BitPat])] = Array( 203 FADD_S -> List(BitPat("b00"),N), 204 FADD_D -> List(BitPat("b00"),N), 205 FSUB_S -> List(BitPat("b01"),N), 206 FSUB_D -> List(BitPat("b01"),N), 207 FMUL_S -> List(BitPat("b00"),N), 208 FMUL_D -> List(BitPat("b00"),N), 209 FMADD_S -> List(BitPat("b00"),Y), 210 FMADD_D -> List(BitPat("b00"),Y), 211 FMSUB_S -> List(BitPat("b01"),Y), 212 FMSUB_D -> List(BitPat("b01"),Y), 213 FNMADD_S-> List(BitPat("b11"),Y), 214 FNMADD_D-> List(BitPat("b11"),Y), 215 FNMSUB_S-> List(BitPat("b10"),Y), 216 FNMSUB_D-> List(BitPat("b10"),Y) 217 ) 218 val fmaDefault = List(BitPat("b??"), N) 219 Seq(ctrl.fmaCmd, ctrl.ren3).zip( 220 DecodeLogic(io.instr, fmaDefault, fmaTable) 221 ).foreach({ 222 case (s, d) => s := d 223 }) 224} 225