1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.decode 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.rocket.DecodeLogic 23import freechips.rocketchip.rocket.Instructions._ 24import xiangshan.backend.decode.isa.bitfield.XSInstBitFields 25import xiangshan.backend.fu.fpu.FPU 26import xiangshan.backend.fu.vector.Bundles.{VSew, VLmul, Category} 27import xiangshan.backend.Bundles.VPUCtrlSignals 28import xiangshan.{FPUCtrlSignals, XSModule} 29 30class FPToVecDecoder(implicit p: Parameters) extends XSModule { 31 val io = IO(new Bundle() { 32 val instr = Input(UInt(32.W)) 33 val vpuCtrl = Output(new VPUCtrlSignals) 34 }) 35 36 val inst = io.instr.asTypeOf(new XSInstBitFields) 37 val fpToVecInsts = Seq( 38 FADD_S, FSUB_S, FADD_D, FSUB_D, 39 FEQ_S, FLT_S, FLE_S, FEQ_D, FLT_D, FLE_D, 40 FMIN_S, FMAX_S, FMIN_D, FMAX_D, 41 FMUL_S, FMUL_D, 42 FDIV_S, FDIV_D, FSQRT_S, FSQRT_D, 43 FMADD_S, FMSUB_S, FNMADD_S, FNMSUB_S, FMADD_D, FMSUB_D, FNMADD_D, FNMSUB_D, 44 FCLASS_S, FCLASS_D, FSGNJ_S, FSGNJ_D, FSGNJX_S, FSGNJX_D, FSGNJN_S, FSGNJN_D, 45 ) 46 val isFpToVecInst = fpToVecInsts.map(io.instr === _).reduce(_ || _) 47 val isFP32Instrs = Seq( 48 FADD_S, FSUB_S, FEQ_S, FLT_S, FLE_S, FMIN_S, FMAX_S, 49 FMUL_S, FDIV_S, FSQRT_S, 50 FMADD_S, FMSUB_S, FNMADD_S, FNMSUB_S, 51 FCLASS_S, FSGNJ_S, FSGNJX_S, FSGNJN_S, 52 ) 53 val isFP32Instr = isFP32Instrs.map(io.instr === _).reduce(_ || _) 54 val isFP64Instrs = Seq( 55 FADD_D, FSUB_D, FEQ_D, FLT_D, FLE_D, FMIN_D, FMAX_D, 56 FMUL_D, FDIV_D, FSQRT_D, 57 FMADD_D, FMSUB_D, FNMADD_D, FNMSUB_D, 58 FCLASS_D, FSGNJ_D, FSGNJX_D, FSGNJN_D, 59 ) 60 val isFP64Instr = isFP64Instrs.map(io.instr === _).reduce(_ || _) 61 val needReverseInsts = fpToVecInsts 62 val needReverseInst = needReverseInsts.map(_ === inst.ALL).reduce(_ || _) 63 io.vpuCtrl := 0.U.asTypeOf(io.vpuCtrl) 64 io.vpuCtrl.fpu.isFpToVecInst := isFpToVecInst 65 io.vpuCtrl.fpu.isFP32Instr := isFP32Instr 66 io.vpuCtrl.fpu.isFP64Instr := isFP64Instr 67 io.vpuCtrl.vill := false.B 68 io.vpuCtrl.vma := true.B 69 io.vpuCtrl.vta := true.B 70 io.vpuCtrl.vsew := Mux(isFP32Instr, VSew.e32, VSew.e64) 71 io.vpuCtrl.vlmul := Mux(isFP32Instr, VLmul.mf4, VLmul.mf2) 72 io.vpuCtrl.vm := inst.VM 73 io.vpuCtrl.nf := inst.NF 74 io.vpuCtrl.needScalaSrc := Category.needScalaSrc(inst.VCATEGORY) 75 io.vpuCtrl.permImmTruncate := Category.permImmTruncate(inst.VCATEGORY) 76 io.vpuCtrl.isReverse := needReverseInst 77 io.vpuCtrl.isExt := false.B 78 io.vpuCtrl.isNarrow := false.B 79 io.vpuCtrl.isDstMask := false.B 80 io.vpuCtrl.isOpMask := false.B 81} 82 83 84class FPDecoder(implicit p: Parameters) extends XSModule{ 85 val io = IO(new Bundle() { 86 val instr = Input(UInt(32.W)) 87 val fpCtrl = Output(new FPUCtrlSignals) 88 }) 89 90 private val inst: XSInstBitFields = io.instr.asTypeOf(new XSInstBitFields) 91 92 def X = BitPat("b?") 93 def N = BitPat("b0") 94 def Y = BitPat("b1") 95 val s = BitPat(FPU.S) 96 val d = BitPat(FPU.D) 97 val i = BitPat(FPU.D) 98 99 val default = List(X,X,X,N,N,N,X,X,X) 100 101 // isAddSub tagIn tagOut fromInt wflags fpWen div sqrt fcvt 102 val single: Array[(BitPat, List[BitPat])] = Array( 103 // IntToFP 104 FMV_W_X -> List(N,i,s,Y,N,Y,N,N,N), 105 FCVT_S_W -> List(N,i,s,Y,Y,Y,N,N,Y), 106 FCVT_S_WU-> List(N,i,s,Y,Y,Y,N,N,Y), 107 FCVT_S_L -> List(N,i,s,Y,Y,Y,N,N,Y), 108 FCVT_S_LU-> List(N,i,s,Y,Y,Y,N,N,Y), 109 // FPToInt 110 FMV_X_W -> List(N,d,i,N,N,N,N,N,N), // dont box result of fmv.fp.int 111 FCLASS_S -> List(N,s,i,N,N,N,N,N,N), 112 FCVT_W_S -> List(N,s,i,N,Y,N,N,N,Y), 113 FCVT_WU_S-> List(N,s,i,N,Y,N,N,N,Y), 114 FCVT_L_S -> List(N,s,i,N,Y,N,N,N,Y), 115 FCVT_LU_S-> List(N,s,i,N,Y,N,N,N,Y), 116 FEQ_S -> List(N,s,i,N,Y,N,N,N,N), 117 FLT_S -> List(N,s,i,N,Y,N,N,N,N), 118 FLE_S -> List(N,s,i,N,Y,N,N,N,N), 119 // FPToFP 120 FSGNJ_S -> List(N,s,s,N,N,Y,N,N,N), 121 FSGNJN_S -> List(N,s,s,N,N,Y,N,N,N), 122 FSGNJX_S -> List(N,s,s,N,N,Y,N,N,N), 123 FMIN_S -> List(N,s,s,N,Y,Y,N,N,N), 124 FMAX_S -> List(N,s,s,N,Y,Y,N,N,N), 125 FADD_S -> List(Y,s,s,N,Y,Y,N,N,N), 126 FSUB_S -> List(Y,s,s,N,Y,Y,N,N,N), 127 FMUL_S -> List(N,s,s,N,Y,Y,N,N,N), 128 FMADD_S -> List(N,s,s,N,Y,Y,N,N,N), 129 FMSUB_S -> List(N,s,s,N,Y,Y,N,N,N), 130 FNMADD_S -> List(N,s,s,N,Y,Y,N,N,N), 131 FNMSUB_S -> List(N,s,s,N,Y,Y,N,N,N), 132 FDIV_S -> List(N,s,s,N,Y,Y,Y,N,N), 133 FSQRT_S -> List(N,s,s,N,Y,Y,N,Y,N) 134 ) 135 136 137 // isAddSub tagIn tagOut fromInt wflags fpWen div sqrt fcvt 138 val double: Array[(BitPat, List[BitPat])] = Array( 139 FMV_D_X -> List(N,i,d,Y,N,Y,N,N,N), 140 FCVT_D_W -> List(N,i,d,Y,Y,Y,N,N,Y), 141 FCVT_D_WU-> List(N,i,d,Y,Y,Y,N,N,Y), 142 FCVT_D_L -> List(N,i,d,Y,Y,Y,N,N,Y), 143 FCVT_D_LU-> List(N,i,d,Y,Y,Y,N,N,Y), 144 FMV_X_D -> List(N,d,i,N,N,N,N,N,N), 145 FCLASS_D -> List(N,d,i,N,N,N,N,N,N), 146 FCVT_W_D -> List(N,d,i,N,Y,N,N,N,Y), 147 FCVT_WU_D-> List(N,d,i,N,Y,N,N,N,Y), 148 FCVT_L_D -> List(N,d,i,N,Y,N,N,N,Y), 149 FCVT_LU_D-> List(N,d,i,N,Y,N,N,N,Y), 150 FCVT_S_D -> List(N,d,s,N,Y,Y,N,N,Y), 151 FCVT_D_S -> List(N,s,d,N,Y,Y,N,N,Y), 152 FEQ_D -> List(N,d,i,N,Y,N,N,N,N), 153 FLT_D -> List(N,d,i,N,Y,N,N,N,N), 154 FLE_D -> List(N,d,i,N,Y,N,N,N,N), 155 FSGNJ_D -> List(N,d,d,N,N,Y,N,N,N), 156 FSGNJN_D -> List(N,d,d,N,N,Y,N,N,N), 157 FSGNJX_D -> List(N,d,d,N,N,Y,N,N,N), 158 FMIN_D -> List(N,d,d,N,Y,Y,N,N,N), 159 FMAX_D -> List(N,d,d,N,Y,Y,N,N,N), 160 FADD_D -> List(Y,d,d,N,Y,Y,N,N,N), 161 FSUB_D -> List(Y,d,d,N,Y,Y,N,N,N), 162 FMUL_D -> List(N,d,d,N,Y,Y,N,N,N), 163 FMADD_D -> List(N,d,d,N,Y,Y,N,N,N), 164 FMSUB_D -> List(N,d,d,N,Y,Y,N,N,N), 165 FNMADD_D -> List(N,d,d,N,Y,Y,N,N,N), 166 FNMSUB_D -> List(N,d,d,N,Y,Y,N,N,N), 167 FDIV_D -> List(N,d,d,N,Y,Y,Y,N,N), 168 FSQRT_D -> List(N,d,d,N,Y,Y,N,Y,N) 169 ) 170 171 val table = single ++ double 172 173 val decoder = DecodeLogic(io.instr, default, table) 174 175 val ctrl = io.fpCtrl 176 val sigs = Seq( 177 ctrl.isAddSub, ctrl.typeTagIn, ctrl.typeTagOut, 178 ctrl.fromInt, ctrl.wflags, ctrl.fpWen, 179 ctrl.div, ctrl.sqrt, ctrl.fcvt 180 ) 181 sigs.zip(decoder).foreach({case (s, d) => s := d}) 182 ctrl.typ := inst.TYP 183 ctrl.fmt := inst.FMT 184 ctrl.rm := inst.RM 185 186 val fmaTable: Array[(BitPat, List[BitPat])] = Array( 187 FADD_S -> List(BitPat("b00"),N), 188 FADD_D -> List(BitPat("b00"),N), 189 FSUB_S -> List(BitPat("b01"),N), 190 FSUB_D -> List(BitPat("b01"),N), 191 FMUL_S -> List(BitPat("b00"),N), 192 FMUL_D -> List(BitPat("b00"),N), 193 FMADD_S -> List(BitPat("b00"),Y), 194 FMADD_D -> List(BitPat("b00"),Y), 195 FMSUB_S -> List(BitPat("b01"),Y), 196 FMSUB_D -> List(BitPat("b01"),Y), 197 FNMADD_S-> List(BitPat("b11"),Y), 198 FNMADD_D-> List(BitPat("b11"),Y), 199 FNMSUB_S-> List(BitPat("b10"),Y), 200 FNMSUB_D-> List(BitPat("b10"),Y) 201 ) 202 val fmaDefault = List(BitPat("b??"), N) 203 Seq(ctrl.fmaCmd, ctrl.ren3).zip( 204 DecodeLogic(io.instr, fmaDefault, fmaTable) 205 ).foreach({ 206 case (s, d) => s := d 207 }) 208} 209