1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.decode 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.rocket.DecodeLogic 23import freechips.rocketchip.rocket.Instructions._ 24import xiangshan.backend.decode.isa.bitfield.XSInstBitFields 25import xiangshan.backend.fu.fpu.FPU 26import xiangshan.backend.fu.vector.Bundles.{VSew, VLmul} 27import xiangshan.backend.Bundles.VPUCtrlSignals 28import xiangshan.{FPUCtrlSignals, XSModule} 29 30class FPToVecDecoder(implicit p: Parameters) extends XSModule { 31 val io = IO(new Bundle() { 32 val instr = Input(UInt(32.W)) 33 val vpuCtrl = Output(new VPUCtrlSignals) 34 }) 35 36 val inst = io.instr.asTypeOf(new XSInstBitFields) 37 val fpToVecInsts = Seq( 38 FADD_S, FSUB_S, FADD_D, FSUB_D, 39 FEQ_S, FLT_S, FLE_S, FEQ_D, FLT_D, FLE_D, 40 FMIN_S, FMAX_S, FMIN_D, FMAX_D, 41 FMUL_S, FMUL_D, 42 FDIV_S, FDIV_D, FSQRT_S, FSQRT_D, 43 FMADD_S, FMSUB_S, FNMADD_S, FNMSUB_S, FMADD_D, FMSUB_D, FNMADD_D, FNMSUB_D, 44 FCLASS_S, FCLASS_D, FSGNJ_S, FSGNJ_D, FSGNJX_S, FSGNJX_D, FSGNJN_S, FSGNJN_D, 45 46 // scalar cvt inst 47 FCVT_W_S, FCVT_WU_S, FCVT_L_S, FCVT_LU_S, 48 FCVT_W_D, FCVT_WU_D, FCVT_L_D, FCVT_LU_D, FCVT_S_D, FCVT_D_S, 49 FCVT_S_H, FCVT_H_S, FCVT_H_D, FCVT_D_H, 50 FMV_X_W, FMV_X_D, FMV_X_H, 51 ) 52 val isFpToVecInst = fpToVecInsts.map(io.instr === _).reduce(_ || _) 53 val isFP32Instrs = Seq( 54 FADD_S, FSUB_S, FEQ_S, FLT_S, FLE_S, FMIN_S, FMAX_S, 55 FMUL_S, FDIV_S, FSQRT_S, 56 FMADD_S, FMSUB_S, FNMADD_S, FNMSUB_S, 57 FCLASS_S, FSGNJ_S, FSGNJX_S, FSGNJN_S, 58 ) 59 val isFP32Instr = isFP32Instrs.map(io.instr === _).reduce(_ || _) 60 val isFP64Instrs = Seq( 61 FADD_D, FSUB_D, FEQ_D, FLT_D, FLE_D, FMIN_D, FMAX_D, 62 FMUL_D, FDIV_D, FSQRT_D, 63 FMADD_D, FMSUB_D, FNMADD_D, FNMSUB_D, 64 FCLASS_D, FSGNJ_D, FSGNJX_D, FSGNJN_D, 65 ) 66 val isFP64Instr = isFP64Instrs.map(io.instr === _).reduce(_ || _) 67 // scalar cvt inst 68 val isSew2Cvts = Seq( 69 FCVT_W_S, FCVT_WU_S, FCVT_L_S, FCVT_LU_S, 70 FCVT_W_D, FCVT_WU_D, FCVT_S_D, FCVT_D_S, 71 FMV_X_W, 72 ) 73 /* 74 The optype for FCVT_D_H and FCVT_H_D is the same, 75 so the two instructions are distinguished by sew. 76 FCVT_H_D:VSew.e64 77 FCVT_D_H:VSew.e16 78 */ 79 val isSew2Cvth = Seq( 80 FCVT_S_H, FCVT_H_S, FCVT_D_H, 81 FMV_X_H, 82 ) 83 val isSew2Cvt32 = isSew2Cvts.map(io.instr === _).reduce(_ || _) 84 val isSew2Cvt16 = isSew2Cvth.map(io.instr === _).reduce(_ || _) 85 val isLmulMf4Cvts = Seq( 86 FCVT_W_S, FCVT_WU_S, 87 FMV_X_W, 88 ) 89 val isLmulMf4Cvt = isLmulMf4Cvts.map(io.instr === _).reduce(_ || _) 90 val needReverseInsts = Seq( 91 FADD_S, FSUB_S, FADD_D, FSUB_D, 92 FEQ_S, FLT_S, FLE_S, FEQ_D, FLT_D, FLE_D, 93 FMIN_S, FMAX_S, FMIN_D, FMAX_D, 94 FMUL_S, FMUL_D, 95 FDIV_S, FDIV_D, FSQRT_S, FSQRT_D, 96 FMADD_S, FMSUB_S, FNMADD_S, FNMSUB_S, FMADD_D, FMSUB_D, FNMADD_D, FNMSUB_D, 97 FCLASS_S, FCLASS_D, FSGNJ_S, FSGNJ_D, FSGNJX_S, FSGNJX_D, FSGNJN_S, FSGNJN_D, 98 ) 99 val needReverseInst = needReverseInsts.map(_ === inst.ALL).reduce(_ || _) 100 io.vpuCtrl := 0.U.asTypeOf(io.vpuCtrl) 101 io.vpuCtrl.fpu.isFpToVecInst := isFpToVecInst 102 io.vpuCtrl.fpu.isFP32Instr := isFP32Instr 103 io.vpuCtrl.fpu.isFP64Instr := isFP64Instr 104 io.vpuCtrl.vill := false.B 105 io.vpuCtrl.vma := true.B 106 io.vpuCtrl.vta := true.B 107 io.vpuCtrl.vsew := Mux(isFP32Instr || isSew2Cvt32, VSew.e32, Mux(isSew2Cvt16, VSew.e16, VSew.e64)) 108 io.vpuCtrl.vlmul := Mux(isFP32Instr || isLmulMf4Cvt, VLmul.mf4, VLmul.mf2) 109 io.vpuCtrl.vm := inst.VM 110 io.vpuCtrl.nf := inst.NF 111 io.vpuCtrl.veew := inst.WIDTH 112 io.vpuCtrl.isReverse := needReverseInst 113 io.vpuCtrl.isExt := false.B 114 io.vpuCtrl.isNarrow := false.B 115 io.vpuCtrl.isDstMask := false.B 116 io.vpuCtrl.isOpMask := false.B 117 io.vpuCtrl.isDependOldvd := false.B 118 io.vpuCtrl.isWritePartVd := false.B 119} 120 121 122class FPDecoder(implicit p: Parameters) extends XSModule{ 123 val io = IO(new Bundle() { 124 val instr = Input(UInt(32.W)) 125 val fpCtrl = Output(new FPUCtrlSignals) 126 }) 127 128 private val inst: XSInstBitFields = io.instr.asTypeOf(new XSInstBitFields) 129 130 def X = BitPat("b?") 131 def N = BitPat("b0") 132 def Y = BitPat("b1") 133 val s = BitPat(FPU.S(0)) 134 val d = BitPat(FPU.D(0)) 135 val i = BitPat(FPU.D(0)) 136 137 val default = List(X,X,X,N,N,N,X,X,X) 138 139 // isAddSub tagIn tagOut fromInt wflags fpWen div sqrt fcvt 140 val single: Array[(BitPat, List[BitPat])] = Array( 141 // IntToFP 142 FMV_W_X -> List(N,i,s,Y,N,Y,N,N,N), 143 FCVT_S_W -> List(N,i,s,Y,Y,Y,N,N,Y), 144 FCVT_S_WU-> List(N,i,s,Y,Y,Y,N,N,Y), 145 FCVT_S_L -> List(N,i,s,Y,Y,Y,N,N,Y), 146 FCVT_S_LU-> List(N,i,s,Y,Y,Y,N,N,Y), 147 // FPToInt 148 FMV_X_W -> List(N,d,i,N,N,N,N,N,N), // dont box result of fmv.fp.int 149 FCLASS_S -> List(N,s,i,N,N,N,N,N,N), 150 FCVT_W_S -> List(N,s,i,N,Y,N,N,N,Y), 151 FCVT_WU_S-> List(N,s,i,N,Y,N,N,N,Y), 152 FCVT_L_S -> List(N,s,i,N,Y,N,N,N,Y), 153 FCVT_LU_S-> List(N,s,i,N,Y,N,N,N,Y), 154 FEQ_S -> List(N,s,i,N,Y,N,N,N,N), 155 FLT_S -> List(N,s,i,N,Y,N,N,N,N), 156 FLE_S -> List(N,s,i,N,Y,N,N,N,N), 157 // FPToFP 158 FSGNJ_S -> List(N,s,s,N,N,Y,N,N,N), 159 FSGNJN_S -> List(N,s,s,N,N,Y,N,N,N), 160 FSGNJX_S -> List(N,s,s,N,N,Y,N,N,N), 161 FMIN_S -> List(N,s,s,N,Y,Y,N,N,N), 162 FMAX_S -> List(N,s,s,N,Y,Y,N,N,N), 163 FADD_S -> List(Y,s,s,N,Y,Y,N,N,N), 164 FSUB_S -> List(Y,s,s,N,Y,Y,N,N,N), 165 FMUL_S -> List(N,s,s,N,Y,Y,N,N,N), 166 FMADD_S -> List(N,s,s,N,Y,Y,N,N,N), 167 FMSUB_S -> List(N,s,s,N,Y,Y,N,N,N), 168 FNMADD_S -> List(N,s,s,N,Y,Y,N,N,N), 169 FNMSUB_S -> List(N,s,s,N,Y,Y,N,N,N), 170 FDIV_S -> List(N,s,s,N,Y,Y,Y,N,N), 171 FSQRT_S -> List(N,s,s,N,Y,Y,N,Y,N) 172 ) 173 174 175 // isAddSub tagIn tagOut fromInt wflags fpWen div sqrt fcvt 176 val double: Array[(BitPat, List[BitPat])] = Array( 177 FMV_D_X -> List(N,i,d,Y,N,Y,N,N,N), 178 FCVT_D_W -> List(N,i,d,Y,Y,Y,N,N,Y), 179 FCVT_D_WU-> List(N,i,d,Y,Y,Y,N,N,Y), 180 FCVT_D_L -> List(N,i,d,Y,Y,Y,N,N,Y), 181 FCVT_D_LU-> List(N,i,d,Y,Y,Y,N,N,Y), 182 FMV_X_D -> List(N,d,i,N,N,N,N,N,N), 183 FCLASS_D -> List(N,d,i,N,N,N,N,N,N), 184 FCVT_W_D -> List(N,d,i,N,Y,N,N,N,Y), 185 FCVT_WU_D-> List(N,d,i,N,Y,N,N,N,Y), 186 FCVT_L_D -> List(N,d,i,N,Y,N,N,N,Y), 187 FCVT_LU_D-> List(N,d,i,N,Y,N,N,N,Y), 188 FCVT_S_D -> List(N,d,s,N,Y,Y,N,N,Y), 189 FCVT_D_S -> List(N,s,d,N,Y,Y,N,N,Y), 190 FEQ_D -> List(N,d,i,N,Y,N,N,N,N), 191 FLT_D -> List(N,d,i,N,Y,N,N,N,N), 192 FLE_D -> List(N,d,i,N,Y,N,N,N,N), 193 FSGNJ_D -> List(N,d,d,N,N,Y,N,N,N), 194 FSGNJN_D -> List(N,d,d,N,N,Y,N,N,N), 195 FSGNJX_D -> List(N,d,d,N,N,Y,N,N,N), 196 FMIN_D -> List(N,d,d,N,Y,Y,N,N,N), 197 FMAX_D -> List(N,d,d,N,Y,Y,N,N,N), 198 FADD_D -> List(Y,d,d,N,Y,Y,N,N,N), 199 FSUB_D -> List(Y,d,d,N,Y,Y,N,N,N), 200 FMUL_D -> List(N,d,d,N,Y,Y,N,N,N), 201 FMADD_D -> List(N,d,d,N,Y,Y,N,N,N), 202 FMSUB_D -> List(N,d,d,N,Y,Y,N,N,N), 203 FNMADD_D -> List(N,d,d,N,Y,Y,N,N,N), 204 FNMSUB_D -> List(N,d,d,N,Y,Y,N,N,N), 205 FDIV_D -> List(N,d,d,N,Y,Y,Y,N,N), 206 FSQRT_D -> List(N,d,d,N,Y,Y,N,Y,N) 207 ) 208 209 val table = single ++ double 210 211 val decoder = DecodeLogic(io.instr, default, table) 212 213 val ctrl = io.fpCtrl 214 val sigs = Seq( 215 ctrl.isAddSub, ctrl.typeTagIn, ctrl.typeTagOut, 216 ctrl.fromInt, ctrl.wflags, ctrl.fpWen, 217 ctrl.div, ctrl.sqrt, ctrl.fcvt 218 ) 219 sigs.zip(decoder).foreach({case (s, d) => s := d}) 220 ctrl.typ := inst.TYP 221 ctrl.fmt := inst.FMT 222 ctrl.rm := inst.RM 223 224 val fmaTable: Array[(BitPat, List[BitPat])] = Array( 225 FADD_S -> List(BitPat("b00"),N), 226 FADD_D -> List(BitPat("b00"),N), 227 FSUB_S -> List(BitPat("b01"),N), 228 FSUB_D -> List(BitPat("b01"),N), 229 FMUL_S -> List(BitPat("b00"),N), 230 FMUL_D -> List(BitPat("b00"),N), 231 FMADD_S -> List(BitPat("b00"),Y), 232 FMADD_D -> List(BitPat("b00"),Y), 233 FMSUB_S -> List(BitPat("b01"),Y), 234 FMSUB_D -> List(BitPat("b01"),Y), 235 FNMADD_S-> List(BitPat("b11"),Y), 236 FNMADD_D-> List(BitPat("b11"),Y), 237 FNMSUB_S-> List(BitPat("b10"),Y), 238 FNMSUB_D-> List(BitPat("b10"),Y) 239 ) 240 val fmaDefault = List(BitPat("b??"), N) 241 Seq(ctrl.fmaCmd, ctrl.ren3).zip( 242 DecodeLogic(io.instr, fmaDefault, fmaTable) 243 ).foreach({ 244 case (s, d) => s := d 245 }) 246} 247