1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.decode 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.rocket.DecodeLogic 23import xiangshan.backend.decode.Instructions._ 24import xiangshan.{FPUCtrlSignals, XSModule} 25 26class FPDecoder(implicit p: Parameters) extends XSModule{ 27 val io = IO(new Bundle() { 28 val instr = Input(UInt(32.W)) 29 val fpCtrl = Output(new FPUCtrlSignals) 30 }) 31 32 def X = BitPat("b?") 33 def N = BitPat("b0") 34 def Y = BitPat("b1") 35 val s = BitPat(S) 36 val d = BitPat(D) 37 val i = BitPat(I) 38 39 val default = List(X,X,X,N,N,N,X,X,X) 40 41 // isAddSub tagIn tagOut fromInt wflags fpWen div sqrt fcvt 42 val single: Array[(BitPat, List[BitPat])] = Array( 43 FMV_W_X -> List(N,s,d,Y,N,Y,N,N,N), 44 FCVT_S_W -> List(N,s,s,Y,Y,Y,N,N,Y), 45 FCVT_S_WU-> List(N,s,s,Y,Y,Y,N,N,Y), 46 FCVT_S_L -> List(N,s,s,Y,Y,Y,N,N,Y), 47 FCVT_S_LU-> List(N,s,s,Y,Y,Y,N,N,Y), 48 FMV_X_W -> List(N,d,i,N,N,N,N,N,N), 49 FCLASS_S -> List(N,s,i,N,N,N,N,N,N), 50 FCVT_W_S -> List(N,s,i,N,Y,N,N,N,Y), 51 FCVT_WU_S-> List(N,s,i,N,Y,N,N,N,Y), 52 FCVT_L_S -> List(N,s,i,N,Y,N,N,N,Y), 53 FCVT_LU_S-> List(N,s,i,N,Y,N,N,N,Y), 54 FEQ_S -> List(N,s,i,N,Y,N,N,N,N), 55 FLT_S -> List(N,s,i,N,Y,N,N,N,N), 56 FLE_S -> List(N,s,i,N,Y,N,N,N,N), 57 FSGNJ_S -> List(N,s,s,N,N,Y,N,N,N), 58 FSGNJN_S -> List(N,s,s,N,N,Y,N,N,N), 59 FSGNJX_S -> List(N,s,s,N,N,Y,N,N,N), 60 FMIN_S -> List(N,s,s,N,Y,Y,N,N,N), 61 FMAX_S -> List(N,s,s,N,Y,Y,N,N,N), 62 FADD_S -> List(Y,s,s,N,Y,Y,N,N,N), 63 FSUB_S -> List(Y,s,s,N,Y,Y,N,N,N), 64 FMUL_S -> List(N,s,s,N,Y,Y,N,N,N), 65 FMADD_S -> List(N,s,s,N,Y,Y,N,N,N), 66 FMSUB_S -> List(N,s,s,N,Y,Y,N,N,N), 67 FNMADD_S -> List(N,s,s,N,Y,Y,N,N,N), 68 FNMSUB_S -> List(N,s,s,N,Y,Y,N,N,N), 69 FDIV_S -> List(N,s,s,N,Y,Y,Y,N,N), 70 FSQRT_S -> List(N,s,s,N,Y,Y,N,Y,N) 71 ) 72 73 74 // isAddSub tagIn tagOut fromInt wflags fpWen div sqrt fcvt 75 val double: Array[(BitPat, List[BitPat])] = Array( 76 FMV_D_X -> List(N,d,d,Y,N,Y,N,N,N), 77 FCVT_D_W -> List(N,d,d,Y,Y,Y,N,N,Y), 78 FCVT_D_WU-> List(N,d,d,Y,Y,Y,N,N,Y), 79 FCVT_D_L -> List(N,d,d,Y,Y,Y,N,N,Y), 80 FCVT_D_LU-> List(N,d,d,Y,Y,Y,N,N,Y), 81 FMV_X_D -> List(N,d,i,N,N,N,N,N,N), 82 FCLASS_D -> List(N,d,i,N,N,N,N,N,N), 83 FCVT_W_D -> List(N,d,i,N,Y,N,N,N,Y), 84 FCVT_WU_D-> List(N,d,i,N,Y,N,N,N,Y), 85 FCVT_L_D -> List(N,d,i,N,Y,N,N,N,Y), 86 FCVT_LU_D-> List(N,d,i,N,Y,N,N,N,Y), 87 FCVT_S_D -> List(N,d,s,N,Y,Y,N,N,Y), 88 FCVT_D_S -> List(N,s,d,N,Y,Y,N,N,Y), 89 FEQ_D -> List(N,d,i,N,Y,N,N,N,N), 90 FLT_D -> List(N,d,i,N,Y,N,N,N,N), 91 FLE_D -> List(N,d,i,N,Y,N,N,N,N), 92 FSGNJ_D -> List(N,d,d,N,N,Y,N,N,N), 93 FSGNJN_D -> List(N,d,d,N,N,Y,N,N,N), 94 FSGNJX_D -> List(N,d,d,N,N,Y,N,N,N), 95 FMIN_D -> List(N,d,d,N,Y,Y,N,N,N), 96 FMAX_D -> List(N,d,d,N,Y,Y,N,N,N), 97 FADD_D -> List(Y,d,d,N,Y,Y,N,N,N), 98 FSUB_D -> List(Y,d,d,N,Y,Y,N,N,N), 99 FMUL_D -> List(N,d,d,N,Y,Y,N,N,N), 100 FMADD_D -> List(N,d,d,N,Y,Y,N,N,N), 101 FMSUB_D -> List(N,d,d,N,Y,Y,N,N,N), 102 FNMADD_D -> List(N,d,d,N,Y,Y,N,N,N), 103 FNMSUB_D -> List(N,d,d,N,Y,Y,N,N,N), 104 FDIV_D -> List(N,d,d,N,Y,Y,Y,N,N), 105 FSQRT_D -> List(N,d,d,N,Y,Y,N,Y,N) 106 ) 107 108 val table = single ++ double 109 110 val decoder = DecodeLogic(io.instr, default, table) 111 112 val ctrl = io.fpCtrl 113 val sigs = Seq( 114 ctrl.isAddSub, ctrl.typeTagIn, ctrl.typeTagOut, 115 ctrl.fromInt, ctrl.wflags, ctrl.fpWen, 116 ctrl.div, ctrl.sqrt, ctrl.fcvt 117 ) 118 sigs.zip(decoder).foreach({case (s, d) => s := d}) 119 ctrl.typ := io.instr(21, 20) 120 ctrl.fmt := io.instr(26, 25) 121 ctrl.rm := io.instr(14, 12) 122 123 val fmaTable: Array[(BitPat, List[BitPat])] = Array( 124 FADD_S -> List(BitPat("b00"),N), 125 FADD_D -> List(BitPat("b00"),N), 126 FSUB_S -> List(BitPat("b01"),N), 127 FSUB_D -> List(BitPat("b01"),N), 128 FMUL_S -> List(BitPat("b00"),N), 129 FMUL_D -> List(BitPat("b00"),N), 130 FMADD_S -> List(BitPat("b00"),Y), 131 FMADD_D -> List(BitPat("b00"),Y), 132 FMSUB_S -> List(BitPat("b01"),Y), 133 FMSUB_D -> List(BitPat("b01"),Y), 134 FNMADD_S-> List(BitPat("b11"),Y), 135 FNMADD_D-> List(BitPat("b11"),Y), 136 FNMSUB_S-> List(BitPat("b10"),Y), 137 FNMSUB_D-> List(BitPat("b10"),Y) 138 ) 139 val fmaDefault = List(BitPat("b??"), N) 140 Seq(ctrl.fmaCmd, ctrl.ren3).zip( 141 DecodeLogic(io.instr, fmaDefault, fmaTable) 142 ).foreach({ 143 case (s, d) => s := d 144 }) 145} 146