1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.decode 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.rocket.DecodeLogic 23import freechips.rocketchip.rocket.Instructions._ 24import xiangshan.backend.decode.isa.bitfield.XSInstBitFields 25import xiangshan.backend.fu.fpu.FPU 26import xiangshan.backend.fu.vector.Bundles.{VSew, VLmul} 27import xiangshan.backend.Bundles.VPUCtrlSignals 28import xiangshan.{FPUCtrlSignals, XSModule} 29 30class FPToVecDecoder(implicit p: Parameters) extends XSModule { 31 val io = IO(new Bundle() { 32 val instr = Input(UInt(32.W)) 33 val vpuCtrl = Output(new VPUCtrlSignals) 34 }) 35 36 val inst = io.instr.asTypeOf(new XSInstBitFields) 37 val fpToVecInsts = Seq( 38 FADD_S, FSUB_S, FADD_D, FSUB_D, FADD_H, FSUB_H, 39 FEQ_S, FLT_S, FLE_S, FEQ_D, FLT_D, FLE_D, FEQ_H, FLT_H, FLE_H, 40 FMIN_S, FMAX_S, FMIN_D, FMAX_D, FMIN_H, FMAX_H, 41 FMUL_S, FMUL_D, FMUL_H, 42 FDIV_S, FDIV_D, FSQRT_S, FSQRT_D, FDIV_H, FSQRT_H, 43 FMADD_S, FMSUB_S, FNMADD_S, FNMSUB_S, FMADD_D, FMSUB_D, FNMADD_D, FNMSUB_D, FMADD_H, FMSUB_H, FNMADD_H, FNMSUB_H, 44 FCLASS_S, FCLASS_D, FSGNJ_S, FSGNJ_D, FSGNJX_S, FSGNJX_D, FSGNJN_S, FSGNJN_D, 45 FCLASS_H, FSGNJ_H, FSGNJX_H, FSGNJN_H, 46 // scalar cvt inst 47 FCVT_W_S, FCVT_WU_S, FCVT_L_S, FCVT_LU_S, 48 FCVT_W_D, FCVT_WU_D, FCVT_L_D, FCVT_LU_D, FCVT_S_D, FCVT_D_S, 49 FCVT_S_H, FCVT_H_S, FCVT_H_D, FCVT_D_H, 50 FMV_X_W, FMV_X_D, FMV_X_H, 51 FCVT_W_H, FCVT_WU_H, FCVT_L_H, FCVT_LU_H, 52 // zfa inst 53 FLEQ_H, FLEQ_S, FLEQ_D, FLTQ_H, FLTQ_S, FLTQ_D, FMINM_H, FMINM_S, FMINM_D, FMAXM_H, FMAXM_S, FMAXM_D, 54 FROUND_H, FROUND_S, FROUND_D, FROUNDNX_H, FROUNDNX_S, FROUNDNX_D, FCVTMOD_W_D, 55 ) 56 val isFpToVecInst = fpToVecInsts.map(io.instr === _).reduce(_ || _) 57 val isFP16Instrs = Seq( 58 // zfa inst 59 FLEQ_H, FLTQ_H, FMINM_H, FMAXM_H, 60 FROUND_H, FROUNDNX_H, 61 ) 62 val isFP16Instr = isFP16Instrs.map(io.instr === _).reduce(_ || _) 63 val isFP32Instrs = Seq( 64 FADD_S, FSUB_S, FEQ_S, FLT_S, FLE_S, FMIN_S, FMAX_S, 65 FMUL_S, FDIV_S, FSQRT_S, 66 FMADD_S, FMSUB_S, FNMADD_S, FNMSUB_S, 67 FCLASS_S, FSGNJ_S, FSGNJX_S, FSGNJN_S, 68 // zfa inst 69 FLEQ_S, FLTQ_S, FMINM_S, FMAXM_S, 70 FROUND_S, FROUNDNX_S, 71 ) 72 val isFP32Instr = isFP32Instrs.map(io.instr === _).reduce(_ || _) 73 val isFP64Instrs = Seq( 74 FADD_D, FSUB_D, FEQ_D, FLT_D, FLE_D, FMIN_D, FMAX_D, 75 FMUL_D, FDIV_D, FSQRT_D, 76 FMADD_D, FMSUB_D, FNMADD_D, FNMSUB_D, 77 FCLASS_D, FSGNJ_D, FSGNJX_D, FSGNJN_D, 78 ) 79 val isFP64Instr = isFP64Instrs.map(io.instr === _).reduce(_ || _) 80 // scalar cvt inst 81 val isSew2Cvts = Seq( 82 FCVT_W_S, FCVT_WU_S, FCVT_L_S, FCVT_LU_S, 83 FCVT_W_D, FCVT_WU_D, FCVT_S_D, FCVT_D_S, 84 FMV_X_W, 85 // zfa inst 86 FCVTMOD_W_D, 87 ) 88 /* 89 The optype for FCVT_D_H and FCVT_H_D is the same, 90 so the two instructions are distinguished by sew. 91 FCVT_H_D:VSew.e64 92 FCVT_D_H:VSew.e16 93 */ 94 val isSew2Cvth = Seq( 95 FCVT_S_H, FCVT_H_S, FCVT_D_H, 96 FMV_X_H, 97 FCVT_W_H, FCVT_L_H, FCVT_H_W, 98 FCVT_H_L, FCVT_H_WU, FCVT_H_LU, 99 FCVT_WU_H, FCVT_LU_H, 100 ) 101 val isSew2Cvt32 = isSew2Cvts.map(io.instr === _).reduce(_ || _) 102 val isSew2Cvt16 = isSew2Cvth.map(io.instr === _).reduce(_ || _) 103 val isLmulMf4Cvts = Seq( 104 FCVT_W_S, FCVT_WU_S, 105 FMV_X_W, 106 ) 107 val isLmulMf4Cvt = isLmulMf4Cvts.map(io.instr === _).reduce(_ || _) 108 val needReverseInsts = Seq( 109 FADD_S, FSUB_S, FADD_D, FSUB_D, FADD_H, FSUB_H, 110 FEQ_S, FLT_S, FLE_S, FEQ_D, FLT_D, FLE_D, FEQ_H, FLT_H, FLE_H, 111 FMIN_S, FMAX_S, FMIN_D, FMAX_D, FMIN_H, FMAX_H, 112 FMUL_S, FMUL_D, FMUL_H, 113 FDIV_S, FDIV_D, FSQRT_S, FSQRT_D, FDIV_H, FSQRT_H, 114 FMADD_S, FMSUB_S, FNMADD_S, FNMSUB_S, FMADD_D, FMSUB_D, FNMADD_D, FNMSUB_D, 115 FMADD_H, FMSUB_H, FNMADD_H, FNMSUB_H, 116 FCLASS_S, FCLASS_D, FSGNJ_S, FSGNJ_D, FSGNJX_S, FSGNJX_D, FSGNJN_S, FSGNJN_D, 117 FCLASS_H, FSGNJ_H, FSGNJX_H, FSGNJN_H, 118 // zfa inst 119 FLEQ_H, FLEQ_S, FLEQ_D, FLTQ_H, FLTQ_S, FLTQ_D, FMINM_H, FMINM_S, FMINM_D, FMAXM_H, FMAXM_S, FMAXM_D, 120 ) 121 val needReverseInst = needReverseInsts.map(_ === inst.ALL).reduce(_ || _) 122 io.vpuCtrl := 0.U.asTypeOf(io.vpuCtrl) 123 io.vpuCtrl.fpu.isFpToVecInst := isFpToVecInst 124 io.vpuCtrl.fpu.isFP32Instr := isFP32Instr 125 io.vpuCtrl.fpu.isFP64Instr := isFP64Instr 126 io.vpuCtrl.vill := false.B 127 io.vpuCtrl.vma := true.B 128 io.vpuCtrl.vta := true.B 129 io.vpuCtrl.vsew := Mux(isFP32Instr || isSew2Cvt32, VSew.e32, Mux(isFP16Instr || isSew2Cvt16, VSew.e16, VSew.e64)) 130 io.vpuCtrl.vlmul := Mux(isFP32Instr || isLmulMf4Cvt, VLmul.mf4, VLmul.mf2) 131 io.vpuCtrl.vm := inst.VM 132 io.vpuCtrl.nf := inst.NF 133 io.vpuCtrl.veew := inst.WIDTH 134 io.vpuCtrl.isReverse := needReverseInst 135 io.vpuCtrl.isExt := false.B 136 io.vpuCtrl.isNarrow := false.B 137 io.vpuCtrl.isDstMask := false.B 138 io.vpuCtrl.isOpMask := false.B 139 io.vpuCtrl.isDependOldvd := false.B 140 io.vpuCtrl.isWritePartVd := false.B 141} 142 143 144class FPDecoder(implicit p: Parameters) extends XSModule{ 145 val io = IO(new Bundle() { 146 val instr = Input(UInt(32.W)) 147 val fpCtrl = Output(new FPUCtrlSignals) 148 }) 149 150 private val inst: XSInstBitFields = io.instr.asTypeOf(new XSInstBitFields) 151 152 def X = BitPat("b?") 153 def T = BitPat("b??") //type 154 def N = BitPat("b0") 155 def Y = BitPat("b1") 156 val s = BitPat(FPU.S(1,0)) 157 val d = BitPat(FPU.D(1,0)) 158 val i = BitPat(FPU.D(1,0)) 159 val h = BitPat(FPU.H(1,0)) 160 161 val default = List(X,T,T,N,N,N,X,X,X) 162 163 // isAddSub tagIn tagOut fromInt wflags fpWen div sqrt fcvt 164 val single: Array[(BitPat, List[BitPat])] = Array( 165 // IntToFP 166 FMV_W_X -> List(N,i,s,Y,N,Y,N,N,N), 167 FCVT_S_W -> List(N,i,s,Y,Y,Y,N,N,Y), 168 FCVT_S_WU-> List(N,i,s,Y,Y,Y,N,N,Y), 169 FCVT_S_L -> List(N,i,s,Y,Y,Y,N,N,Y), 170 FCVT_S_LU-> List(N,i,s,Y,Y,Y,N,N,Y), 171 // FPToInt 172 FMV_X_W -> List(N,d,i,N,N,N,N,N,N), // dont box result of fmv.fp.int 173 FCLASS_S -> List(N,s,i,N,N,N,N,N,N), 174 FCVT_W_S -> List(N,s,i,N,Y,N,N,N,Y), 175 FCVT_WU_S-> List(N,s,i,N,Y,N,N,N,Y), 176 FCVT_L_S -> List(N,s,i,N,Y,N,N,N,Y), 177 FCVT_LU_S-> List(N,s,i,N,Y,N,N,N,Y), 178 FEQ_S -> List(N,s,i,N,Y,N,N,N,N), 179 FLT_S -> List(N,s,i,N,Y,N,N,N,N), 180 FLE_S -> List(N,s,i,N,Y,N,N,N,N), 181 // FPToFP 182 FSGNJ_S -> List(N,s,s,N,N,Y,N,N,N), 183 FSGNJN_S -> List(N,s,s,N,N,Y,N,N,N), 184 FSGNJX_S -> List(N,s,s,N,N,Y,N,N,N), 185 FMIN_S -> List(N,s,s,N,Y,Y,N,N,N), 186 FMAX_S -> List(N,s,s,N,Y,Y,N,N,N), 187 FADD_S -> List(Y,s,s,N,Y,Y,N,N,N), 188 FSUB_S -> List(Y,s,s,N,Y,Y,N,N,N), 189 FMUL_S -> List(N,s,s,N,Y,Y,N,N,N), 190 FMADD_S -> List(N,s,s,N,Y,Y,N,N,N), 191 FMSUB_S -> List(N,s,s,N,Y,Y,N,N,N), 192 FNMADD_S -> List(N,s,s,N,Y,Y,N,N,N), 193 FNMSUB_S -> List(N,s,s,N,Y,Y,N,N,N), 194 FDIV_S -> List(N,s,s,N,Y,Y,Y,N,N), 195 FSQRT_S -> List(N,s,s,N,Y,Y,N,Y,N) 196 ) 197 198 199 // isAddSub tagIn tagOut fromInt wflags fpWen div sqrt fcvt 200 val double: Array[(BitPat, List[BitPat])] = Array( 201 FMV_D_X -> List(N,i,d,Y,N,Y,N,N,N), 202 FCVT_D_W -> List(N,i,d,Y,Y,Y,N,N,Y), 203 FCVT_D_WU-> List(N,i,d,Y,Y,Y,N,N,Y), 204 FCVT_D_L -> List(N,i,d,Y,Y,Y,N,N,Y), 205 FCVT_D_LU-> List(N,i,d,Y,Y,Y,N,N,Y), 206 FMV_X_D -> List(N,d,i,N,N,N,N,N,N), 207 FCLASS_D -> List(N,d,i,N,N,N,N,N,N), 208 FCVT_W_D -> List(N,d,i,N,Y,N,N,N,Y), 209 FCVT_WU_D-> List(N,d,i,N,Y,N,N,N,Y), 210 FCVT_L_D -> List(N,d,i,N,Y,N,N,N,Y), 211 FCVT_LU_D-> List(N,d,i,N,Y,N,N,N,Y), 212 FCVT_S_D -> List(N,d,s,N,Y,Y,N,N,Y), 213 FCVT_D_S -> List(N,s,d,N,Y,Y,N,N,Y), 214 FEQ_D -> List(N,d,i,N,Y,N,N,N,N), 215 FLT_D -> List(N,d,i,N,Y,N,N,N,N), 216 FLE_D -> List(N,d,i,N,Y,N,N,N,N), 217 FSGNJ_D -> List(N,d,d,N,N,Y,N,N,N), 218 FSGNJN_D -> List(N,d,d,N,N,Y,N,N,N), 219 FSGNJX_D -> List(N,d,d,N,N,Y,N,N,N), 220 FMIN_D -> List(N,d,d,N,Y,Y,N,N,N), 221 FMAX_D -> List(N,d,d,N,Y,Y,N,N,N), 222 FADD_D -> List(Y,d,d,N,Y,Y,N,N,N), 223 FSUB_D -> List(Y,d,d,N,Y,Y,N,N,N), 224 FMUL_D -> List(N,d,d,N,Y,Y,N,N,N), 225 FMADD_D -> List(N,d,d,N,Y,Y,N,N,N), 226 FMSUB_D -> List(N,d,d,N,Y,Y,N,N,N), 227 FNMADD_D -> List(N,d,d,N,Y,Y,N,N,N), 228 FNMSUB_D -> List(N,d,d,N,Y,Y,N,N,N), 229 FDIV_D -> List(N,d,d,N,Y,Y,Y,N,N), 230 FSQRT_D -> List(N,d,d,N,Y,Y,N,Y,N) 231 ) 232 233 val half : Array[(BitPat, List[BitPat])] = Array( 234 // IntToFP 235 FMV_H_X -> List(N,i,h,Y,N,Y,N,N,N), 236 FCVT_H_W -> List(N,i,h,Y,Y,Y,N,N,Y), 237 FCVT_H_WU-> List(N,i,h,Y,Y,Y,N,N,Y), 238 FCVT_H_L -> List(N,i,h,Y,Y,Y,N,N,Y), 239 FCVT_H_LU-> List(N,i,h,Y,Y,Y,N,N,Y), 240 // FPToInt 241 FMV_X_H -> List(N,h,i,N,N,N,N,N,N), // d or h ?? 242 FCLASS_H -> List(N,h,i,N,N,N,N,N,N), 243 FCVT_W_H -> List(N,h,i,N,Y,N,N,N,Y), 244 FCVT_WU_H-> List(N,h,i,N,Y,N,N,N,Y), 245 FCVT_L_H -> List(N,h,i,N,Y,N,N,N,Y), 246 FCVT_LU_H-> List(N,h,i,N,Y,N,N,N,Y), 247 FEQ_H -> List(N,h,i,N,Y,N,N,N,N), 248 FLT_H -> List(N,h,i,N,Y,N,N,N,N), 249 FLE_H -> List(N,h,i,N,Y,N,N,N,N), 250 // FPToFP 251 FSGNJ_H -> List(N,h,h,N,N,Y,N,N,N), 252 FSGNJN_H -> List(N,h,h,N,N,Y,N,N,N), 253 FSGNJX_H -> List(N,h,h,N,N,Y,N,N,N), 254 FMIN_H -> List(N,h,h,N,Y,Y,N,N,N), 255 FMAX_H -> List(N,h,h,N,Y,Y,N,N,N), 256 FADD_H -> List(Y,h,h,N,Y,Y,N,N,N), 257 FSUB_H -> List(Y,h,h,N,Y,Y,N,N,N), 258 FMUL_H -> List(N,h,h,N,Y,Y,N,N,N), 259 FMADD_H -> List(N,h,h,N,Y,Y,N,N,N), 260 FMSUB_H -> List(N,h,h,N,Y,Y,N,N,N), 261 FNMADD_H -> List(N,h,h,N,Y,Y,N,N,N), 262 FNMSUB_H -> List(N,h,h,N,Y,Y,N,N,N), 263 FDIV_H -> List(N,h,h,N,Y,Y,Y,N,N), 264 FSQRT_H -> List(N,h,h,N,Y,Y,N,Y,N) 265 ) 266 267 val table = single ++ double ++ half 268 269 val decoder = DecodeLogic(io.instr, default, table) 270 271 val ctrl = io.fpCtrl 272 val sigs = Seq( 273 ctrl.isAddSub, ctrl.typeTagIn, ctrl.typeTagOut, 274 ctrl.fromInt, ctrl.wflags, ctrl.fpWen, 275 ctrl.div, ctrl.sqrt, ctrl.fcvt 276 ) 277 sigs.zip(decoder).foreach({case (s, d) => s := d}) 278 ctrl.typ := inst.TYP 279 ctrl.fmt := inst.FMT 280 ctrl.rm := inst.RM 281 282 val fmaTable: Array[(BitPat, List[BitPat])] = Array( 283 FADD_S -> List(BitPat("b00"),N), 284 FADD_D -> List(BitPat("b00"),N), 285 FADD_H -> List(BitPat("b00"),N), 286 FSUB_S -> List(BitPat("b01"),N), 287 FSUB_D -> List(BitPat("b01"),N), 288 FSUB_H -> List(BitPat("b01"),N), 289 FMUL_S -> List(BitPat("b00"),N), 290 FMUL_D -> List(BitPat("b00"),N), 291 FMUL_H -> List(BitPat("b00"),N), 292 FMADD_S -> List(BitPat("b00"),Y), 293 FMADD_D -> List(BitPat("b00"),Y), 294 FMADD_H -> List(BitPat("b00"),Y), 295 FMSUB_S -> List(BitPat("b01"),Y), 296 FMSUB_D -> List(BitPat("b01"),Y), 297 FMSUB_H -> List(BitPat("b01"),Y), 298 FNMADD_S-> List(BitPat("b11"),Y), 299 FNMADD_D-> List(BitPat("b11"),Y), 300 FNMADD_H-> List(BitPat("b11"),Y), 301 FNMSUB_S-> List(BitPat("b10"),Y), 302 FNMSUB_D-> List(BitPat("b10"),Y) 303 FNMSUB_D-> List(BitPat("b10"),Y), 304 FNMSUB_H-> List(BitPat("b10"),Y) 305 ) 306 val fmaDefault = List(BitPat("b??"), N) 307 Seq(ctrl.fmaCmd, ctrl.ren3).zip( 308 DecodeLogic(io.instr, fmaDefault, fmaTable) 309 ).foreach({ 310 case (s, d) => s := d 311 }) 312} 313