1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* 4* XiangShan is licensed under Mulan PSL v2. 5* You can use this software according to the terms and conditions of the Mulan PSL v2. 6* You may obtain a copy of Mulan PSL v2 at: 7* http://license.coscl.org.cn/MulanPSL2 8* 9* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 10* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 11* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 12* 13* See the Mulan PSL v2 for more details. 14***************************************************************************************/ 15 16package top 17 18import chisel3._ 19import chipsalliance.rocketchip.config 20import device._ 21import freechips.rocketchip.amba.axi4.{AXI4EdgeParameters, AXI4MasterNode, AXI4Xbar} 22import freechips.rocketchip.diplomacy.{AddressSet, InModuleBody, LazyModule, LazyModuleImp} 23 24class SimMMIO(edge: AXI4EdgeParameters)(implicit p: config.Parameters) extends LazyModule { 25 26 val node = AXI4MasterNode(List(edge.master)) 27 28 val flash = LazyModule(new AXI4Flash(Seq(AddressSet(0x10000000L, 0xfffffff)))) 29 val uart = LazyModule(new AXI4UART(Seq(AddressSet(0x40600000L, 0xf)))) 30 val vga = LazyModule(new AXI4VGA( 31 sim = false, 32 fbAddress = Seq(AddressSet(0x50000000L, 0x3fffffL)), 33 ctrlAddress = Seq(AddressSet(0x40001000L, 0x7L)) 34 )) 35 val sd = LazyModule(new AXI4DummySD(Seq(AddressSet(0x40002000L, 0xfff)))) 36 val intrGen = LazyModule(new AXI4IntrGenerator(Seq(AddressSet(0x40070000L, 0x0000ffffL)))) 37 38 val axiBus = AXI4Xbar() 39 40 uart.node := axiBus 41 vga.node :*= axiBus 42 flash.node := axiBus 43 sd.node := axiBus 44 intrGen.node := axiBus 45 46 axiBus := node 47 48 val io_axi4 = InModuleBody { 49 node.makeIOs() 50 } 51 52 def connectToSoC(soc: HaveAXI4PeripheralPort) = { 53 io_axi4 <> soc.peripheral 54 } 55 56 lazy val module = new LazyModuleImp(this){ 57 val io = IO(new Bundle() { 58 val uart = new UARTIO 59 val interrupt = new IntrGenIO 60 }) 61 io.uart <> uart.module.io.extra.get 62 io.interrupt <> intrGen.module.io.extra.get 63 } 64 65} 66