xref: /XiangShan/src/main/scala/xiangshan/XSDts.scala (revision c6d439803a044ea209139672b25e35fe8d7f4aa0) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3*
4* XiangShan is licensed under Mulan PSL v2.
5* You can use this software according to the terms and conditions of the Mulan PSL v2.
6* You may obtain a copy of Mulan PSL v2 at:
7*          http://license.coscl.org.cn/MulanPSL2
8*
9* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
10* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
11* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
12*
13* See the Mulan PSL v2 for more details.
14***************************************************************************************/
15
16// See LICENSE.SiFive for license details.
17
18package xiangshan
19
20import freechips.rocketchip.diplomacy._
21
22trait HasXSDts {
23  this: XSCore =>
24
25  val device: SimpleDevice = new SimpleDevice("cpu", Seq("ICT,xiangshan", "riscv")) {
26    override def parent: Some[Device] = Some(ResourceAnchors.cpus)
27
28    def cpuProperties: PropertyMap = Map(
29      "device_type" -> "cpu".asProperty,
30      "status" -> "okay".asProperty,
31      "clock-frequency" -> 0.asProperty,
32      "riscv,isa" -> "rv64imafdc".asProperty,
33      "timebase-frequency" -> 1000000.asProperty
34    )
35
36    def tileProperties: PropertyMap = {
37      val dcache = Map(
38        "d-cache-block-size" -> dcacheParameters.blockBytes.asProperty,
39        "d-cache-sets" -> dcacheParameters.nSets.asProperty,
40        "d-cache-size" -> (dcacheParameters.nSets * dcacheParameters.nWays * dcacheParameters.blockBytes).asProperty
41      )
42
43      val icache = Map(
44        "i-cache-block-size" -> icacheParameters.blockBytes.asProperty,
45        "i-cache-sets" -> icacheParameters.nSets.asProperty,
46        "i-cache-size" -> (icacheParameters.nSets * icacheParameters.nWays * icacheParameters.blockBytes).asProperty
47      )
48
49      val dtlb = Map(
50        "d-tlb-size" -> TlbEntrySize.asProperty,
51        "d-tlb-sets" -> 1.asProperty
52      )
53
54      val itlb = Map(
55        "i-tlb-size" -> TlbEntrySize.asProperty,
56        "i-tlb-sets" -> 1.asProperty
57      )
58
59      val mmu = Map(
60        "tlb-split" -> Nil,
61        "mmu-type" -> s"riscv,sv$VAddrBits".asProperty
62      )
63
64      val pmp = Nil
65
66      dcache ++ icache ++ dtlb ++ itlb ++ mmu ++ pmp
67    }
68
69    def nextLevelCacheProperty: PropertyOption = {
70      println(memBlock)
71      val outer = memBlock.dcache.clientNode.edges.out.flatMap(_.manager.managers)
72        .filter(_.supportsAcquireB)
73        .flatMap(_.resources.headOption)
74        .map(_.owner.label)
75        .distinct
76      if (outer.isEmpty) None
77      else Some("next-level-cache" -> outer.map(l => ResourceReference(l)).toList)
78    }
79
80    override def describe(resources: ResourceBindings): Description = {
81      val Description(name, mapping) = super.describe(resources)
82      Description(name, mapping ++ cpuProperties ++ nextLevelCacheProperty ++ tileProperties)
83    }
84  }
85  ResourceBinding {
86    Resource(device, "reg").bind(ResourceAddress(hardId))
87  }
88}
89