xref: /XiangShan/src/test/scala/top/SimTop.scala (revision f320e0f01bd645f0a3045a8a740e60dd770734a9) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package top
18
19import chipsalliance.rocketchip.config.{Config, Parameters}
20import chisel3.stage.ChiselGeneratorAnnotation
21import chisel3._
22import device.{AXI4RAMWrapper, UARTIO}
23import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
24import utils.GTimer
25import xiangshan.{DebugOptions, DebugOptionsKey, PerfInfoIO}
26
27class LogCtrlIO extends Bundle {
28  val log_begin, log_end = Input(UInt(64.W))
29  val log_level = Input(UInt(64.W)) // a cpp uint
30}
31
32class SimTop(implicit p: Parameters) extends Module {
33  val debugOpts = p(DebugOptionsKey)
34  val useDRAMSim = debugOpts.UseDRAMSim
35
36  val l_soc = LazyModule(new XSTopWithoutDMA())
37  val soc = Module(l_soc.module)
38
39  val l_simMMIO = LazyModule(new SimMMIO(l_soc.peripheralNode.in.head._2))
40  val simMMIO = Module(l_simMMIO.module)
41  l_simMMIO.connectToSoC(l_soc)
42
43  if(!useDRAMSim){
44    val l_simAXIMem = LazyModule(new AXI4RAMWrapper(
45      l_soc.memAXI4SlaveNode, 8L * 1024 * 1024 * 1024, useBlackBox = true
46    ))
47    val simAXIMem = Module(l_simAXIMem.module)
48    l_simAXIMem.connectToSoC(l_soc)
49  }
50
51  soc.io.clock := clock.asBool()
52  soc.io.reset := reset.asBool()
53  soc.io.extIntrs := simMMIO.io.interrupt.intrVec
54
55  val io = IO(new Bundle(){
56    val logCtrl = new LogCtrlIO
57    val perfInfo = new PerfInfoIO
58    val uart = new UARTIO
59    val memAXI = if(useDRAMSim) l_soc.memory.cloneType else null
60  })
61
62  simMMIO.io.uart <> io.uart
63
64  if(useDRAMSim){
65    io.memAXI <> l_soc.memory
66  }
67
68  if (debugOpts.EnableDebug || debugOpts.EnablePerfDebug) {
69    val timer = GTimer()
70    val logEnable = (timer >= io.logCtrl.log_begin) && (timer < io.logCtrl.log_end)
71    ExcitingUtils.addSource(logEnable, "DISPLAY_LOG_ENABLE")
72    ExcitingUtils.addSource(timer, "logTimestamp")
73  }
74
75  if (debugOpts.EnablePerfDebug) {
76    val clean = io.perfInfo.clean
77    val dump = io.perfInfo.dump
78    ExcitingUtils.addSource(clean, "XSPERF_CLEAN")
79    ExcitingUtils.addSource(dump, "XSPERF_DUMP")
80  }
81
82  // Check and dispaly all source and sink connections
83  ExcitingUtils.fixConnections()
84  ExcitingUtils.checkAndDisplay()
85}
86
87object SimTop extends App {
88
89  override def main(args: Array[String]): Unit = {
90    val (config, firrtlOpts) = ArgParser.parse(args, fpga = false)
91    // generate verilog
92    XiangShanStage.execute(
93      firrtlOpts,
94      Seq(
95        ChiselGeneratorAnnotation(() => new SimTop()(config))
96      )
97    )
98  }
99}
100