1package xiangshan.backend.exu 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import xiangshan.backend.BackendParams 7import xiangshan.backend.Bundles.{ExuBypassBundle, ExuInput, ExuOutput} 8import xiangshan.backend.datapath.DataConfig.DataConfig 9import xiangshan.backend.datapath.RdConfig._ 10import xiangshan.backend.datapath.WbConfig.{IntWB, PregWB, VfWB} 11import xiangshan.backend.datapath.{DataConfig, WakeUpConfig} 12import xiangshan.backend.fu.{FuConfig, FuType} 13import xiangshan.backend.issue.{IntScheduler, SchedulerType, VfScheduler} 14 15case class ExeUnitParams( 16 name : String, 17 fuConfigs : Seq[FuConfig], 18 wbPortConfigs : Seq[PregWB], 19 rfrPortConfigs: Seq[Seq[RdConfig]], 20 fakeUnit : Boolean = false, 21)( 22 implicit 23 val schdType: SchedulerType, 24) { 25 // calculated configs 26 var iqWakeUpSourcePairs: Seq[WakeUpConfig] = Seq() 27 var iqWakeUpSinkPairs: Seq[WakeUpConfig] = Seq() 28 // used in bypass to select data of exu output 29 var exuIdx: Int = -1 30 var backendParam: BackendParams = null 31 32 val numIntSrc: Int = fuConfigs.map(_.numIntSrc).max 33 val numFpSrc: Int = fuConfigs.map(_.numFpSrc).max 34 val numVecSrc: Int = fuConfigs.map(_.numVecSrc).max 35 val numVfSrc: Int = fuConfigs.map(_.numVfSrc).max 36 val numRegSrc: Int = fuConfigs.map(_.numRegSrc).max 37 val numSrc: Int = fuConfigs.map(_.numSrc).max 38 val dataBitsMax: Int = fuConfigs.map(_.dataBits).max 39 val readIntRf: Boolean = numIntSrc > 0 40 val readFpRf: Boolean = numFpSrc > 0 41 val readVecRf: Boolean = numVecSrc > 0 42 val writeIntRf: Boolean = fuConfigs.map(_.writeIntRf).reduce(_ || _) 43 val writeFpRf: Boolean = fuConfigs.map(_.writeFpRf).reduce(_ || _) 44 val writeVecRf: Boolean = fuConfigs.map(_.writeVecRf).reduce(_ || _) 45 val writeVfRf: Boolean = writeFpRf || writeVecRf 46 val writeFflags: Boolean = fuConfigs.map(_.writeFflags).reduce(_ || _) 47 val writeVxsat: Boolean = fuConfigs.map(_.writeVxsat).reduce(_ || _) 48 val hasNoDataWB: Boolean = fuConfigs.map(_.hasNoDataWB).reduce(_ || _) 49 val hasRedirect: Boolean = fuConfigs.map(_.hasRedirect).reduce(_ || _) 50 val hasPredecode: Boolean = fuConfigs.map(_.hasPredecode).reduce(_ || _) 51 val exceptionOut: Seq[Int] = fuConfigs.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted 52 val hasLoadError: Boolean = fuConfigs.map(_.hasLoadError).reduce(_ || _) 53 val flushPipe: Boolean = fuConfigs.map(_.flushPipe).reduce(_ || _) 54 val replayInst: Boolean = fuConfigs.map(_.replayInst).reduce(_ || _) 55 val trigger: Boolean = fuConfigs.map(_.trigger).reduce(_ || _) 56 val needExceptionGen: Boolean = exceptionOut.nonEmpty || flushPipe || replayInst || trigger 57 val needPc: Boolean = fuConfigs.map(_.needPc).reduce(_ || _) 58 val needTarget: Boolean = fuConfigs.map(_.needTargetPc).reduce(_ || _) 59 val needPdInfo: Boolean = fuConfigs.map(_.needPdInfo).reduce(_ || _) 60 val needSrcFrm: Boolean = fuConfigs.map(_.needSrcFrm).reduce(_ || _) 61 val needFPUCtrl: Boolean = fuConfigs.map(_.needFPUCtrl).reduce(_ || _) 62 val needVPUCtrl: Boolean = fuConfigs.map(_.needVecCtrl).reduce(_ || _) 63 val isHighestWBPriority: Boolean = wbPortConfigs.forall(_.priority == 0) 64 65 def rdPregIdxWidth: Int = { 66 this.pregRdDataCfgSet.map(dataCfg => backendParam.getPregParams(dataCfg).addrWidth).fold(0)(_ max _) 67 } 68 69 def wbPregIdxWidth: Int = { 70 this.pregWbDataCfgSet.map(dataCfg => backendParam.getPregParams(dataCfg).addrWidth).fold(0)(_ max _) 71 } 72 73 val writeIntFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeIntRf) 74 val writeVfFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeFpRf || x.writeVecRf) 75 76 /** 77 * Check if this exu has certain latency 78 */ 79 def latencyCertain: Boolean = fuConfigs.map(x => x.latency.latencyVal.nonEmpty).reduce(_ && _) 80 def intLatencyCertain: Boolean = writeIntFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 81 def vfLatencyCertain: Boolean = writeVfFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 82 // only load use it 83 def hasUncertainLatencyVal: Boolean = fuConfigs.map(x => x.latency.uncertainLatencyVal.nonEmpty).reduce(_ || _) 84 85 /** 86 * Get mapping from FuType to Latency value. 87 * If both [[latencyCertain]] and [[hasUncertainLatencyVal]] are false, get empty [[Map]] 88 * 89 * @return Map[ [[BigInt]], Latency] 90 */ 91 def fuLatencyMap: Map[FuType.OHType, Int] = { 92 if (latencyCertain) 93 fuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 94 else if (hasUncertainLatencyVal) 95 fuConfigs.map(x => (x.fuType, x.latency.uncertainLatencyVal)).toMap.filter(_._2.nonEmpty).map(x => (x._1, x._2.get)) 96 else 97 Map() 98 } 99 100 /** 101 * Get set of latency of function units. 102 * If both [[latencyCertain]] and [[hasUncertainLatencyVal]] are false, get empty [[Set]] 103 * 104 * @return Set[Latency] 105 */ 106 def fuLatancySet: Set[Int] = fuLatencyMap.values.toSet 107 108 def latencyValMax: Int = fuLatancySet.fold(0)(_ max _) 109 110 def intFuLatencyMap: Map[FuType.OHType, Int] = { 111 if (intLatencyCertain) 112 writeIntFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 113 else 114 Map() 115 } 116 117 def intLatencyValMax: Int = intFuLatencyMap.values.fold(0)(_ max _) 118 119 def vfFuLatencyMap: Map[FuType.OHType, Int] = { 120 if (vfLatencyCertain) 121 writeVfFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 122 else 123 Map() 124 } 125 126 def vfLatencyValMax: Int = vfFuLatencyMap.values.fold(0)(_ max _) 127 128 /** 129 * Check if this exu has fixed latency 130 */ 131 def isFixedLatency: Boolean = { 132 if (latencyCertain) 133 return fuConfigs.map(x => x.latency.latencyVal.get == fuConfigs.head.latency.latencyVal.get).reduce(_ && _) 134 false 135 } 136 137 def hasCSR: Boolean = fuConfigs.map(_.isCsr).reduce(_ || _) 138 139 def hasFence: Boolean = fuConfigs.map(_.isFence).reduce(_ || _) 140 141 def hasBrhFu = fuConfigs.map(_.fuType == FuType.brh).reduce(_ || _) 142 143 def hasJmpFu = fuConfigs.map(_.fuType == FuType.jmp).reduce(_ || _) 144 145 def hasLoadFu = fuConfigs.map(_.name == "ldu").reduce(_ || _) 146 147 def hasVLoadFu = fuConfigs.map(_.fuType == FuType.vldu).reduce(_ || _) 148 149 def hasVStoreFu = fuConfigs.map(_.fuType == FuType.vstu).reduce(_ || _) 150 151 def hasStoreAddrFu = fuConfigs.map(_.name == "sta").reduce(_ || _) 152 153 def hasStdFu = fuConfigs.map(_.name == "std").reduce(_ || _) 154 155 def hasMemAddrFu = hasLoadFu || hasStoreAddrFu || hasVLoadFu || hasHyldaFu || hasHystaFu || hasVLoadFu || hasVStoreFu 156 157 def hasHyldaFu = fuConfigs.map(_.name == "hylda").reduce(_ || _) 158 159 def hasHystaFu = fuConfigs.map(_.name == "hysta").reduce(_ || _) 160 161 def hasVecFu = fuConfigs.map(x => FuConfig.VecArithFuConfigs.contains(x)).reduce(_ || _) 162 163 def getSrcDataType(srcIdx: Int): Set[DataConfig] = { 164 fuConfigs.map(_.getSrcDataType(srcIdx)).reduce(_ ++ _) 165 } 166 167 def immType: Set[UInt] = fuConfigs.map(x => x.immType).reduce(_ ++ _) 168 169 def getWBSource: SchedulerType = { 170 schdType 171 } 172 173 def hasCrossWb: Boolean = { 174 schdType match { 175 case IntScheduler() => writeFpRf || writeVecRf 176 case VfScheduler() => writeIntRf 177 case _ => false 178 } 179 } 180 181 def canAccept(fuType: UInt): Bool = { 182 Cat(fuConfigs.map(_.fuType.U === fuType)).orR 183 } 184 185 def hasUncertainLatency: Boolean = fuConfigs.map(_.latency.latencyVal.isEmpty).reduce(_ || _) 186 187 def bindBackendParam(param: BackendParams): Unit = { 188 backendParam = param 189 } 190 191 def updateIQWakeUpConfigs(cfgs: Seq[WakeUpConfig]) = { 192 this.iqWakeUpSourcePairs = cfgs.filter(_.source.name == this.name) 193 this.iqWakeUpSinkPairs = cfgs.filter(_.sink.name == this.name) 194 if (this.isIQWakeUpSource) { 195 require(!this.hasUncertainLatency || hasLoadFu || hasHyldaFu, s"${this.name} is a not-LDU IQ wake up source , but has UncertainLatency") 196 } 197 } 198 199 def updateExuIdx(idx: Int): Unit = { 200 this.exuIdx = idx 201 } 202 203 def isIQWakeUpSource = this.iqWakeUpSourcePairs.nonEmpty 204 205 def isIQWakeUpSink = this.iqWakeUpSinkPairs.nonEmpty 206 207 def getIntWBPort = { 208 wbPortConfigs.collectFirst { 209 case x: IntWB => x 210 } 211 } 212 213 def getVfWBPort = { 214 wbPortConfigs.collectFirst { 215 case x: VfWB => x 216 } 217 } 218 219 /** 220 * Get the [[DataConfig]] that this exu need to read 221 */ 222 def pregRdDataCfgSet: Set[DataConfig] = { 223 this.rfrPortConfigs.flatten.map(_.getDataConfig).toSet 224 } 225 226 /** 227 * Get the [[DataConfig]] that this exu need to write 228 */ 229 def pregWbDataCfgSet: Set[DataConfig] = { 230 this.wbPortConfigs.map(_.dataCfg).toSet 231 } 232 233 def getRfReadDataCfgSet: Seq[Set[DataConfig]] = { 234 val fuSrcsCfgSet: Seq[Seq[Set[DataConfig]]] = fuConfigs.map(_.getRfReadDataCfgSet) 235 val alignedFuSrcsCfgSet: Seq[Seq[Set[DataConfig]]] = fuSrcsCfgSet.map(x => x ++ Seq.fill(numRegSrc - x.length)(Set[DataConfig]())) 236 237 val exuSrcsCfgSet = alignedFuSrcsCfgSet.reduce((x, y) => (x zip y).map { case (cfg1, cfg2) => cfg1 union cfg2 }) 238 239 exuSrcsCfgSet 240 } 241 242 /** 243 * Get the [[DataConfig]] mapped indices of source data of exu 244 * 245 * @example 246 * {{{ 247 * fuCfg.srcData = Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()) 248 * getRfReadSrcIdx(VecData()) = Seq(0, 1, 2) 249 * getRfReadSrcIdx(MaskSrcData()) = Seq(3) 250 * getRfReadSrcIdx(VConfigData()) = Seq(4) 251 * }}} 252 * @return Map[DataConfig -> Seq[indices]] 253 */ 254 def getRfReadSrcIdx: Map[DataConfig, Seq[Int]] = { 255 val dataCfgs = DataConfig.RegSrcDataSet 256 val rfRdDataCfgSet = this.getRfReadDataCfgSet 257 dataCfgs.toSeq.map { cfg => 258 ( 259 cfg, 260 rfRdDataCfgSet.zipWithIndex.map { case (set, srcIdx) => 261 if (set.contains(cfg)) 262 Option(srcIdx) 263 else 264 None 265 }.filter(_.nonEmpty).map(_.get) 266 ) 267 }.toMap 268 } 269 270 def genExuModule(implicit p: Parameters): ExeUnit = { 271 new ExeUnit(this) 272 } 273 274 def genExuInputBundle(implicit p: Parameters): ExuInput = { 275 new ExuInput(this) 276 } 277 278 def genExuOutputBundle(implicit p: Parameters): ExuOutput = { 279 new ExuOutput(this) 280 } 281 282 def genExuBypassBundle(implicit p: Parameters): ExuBypassBundle = { 283 new ExuBypassBundle(this) 284 } 285} 286