area(EXU): add parameter `needCopySrc` in FuConfig (#4063)

area(Backend): merge pcMem and pcTargetMem

feat(backend): NewDispatch

area(IssueQueue): encode exuOH as UInt to reduce storage (#4033)

feat(dbltrp) : add support for critical error (#3793)

Backend: remove useless loadCancel for fix timing (#3374)

ExeUnitParams: add 1 cycle delay when vf exe units write back to fp regfile

Backend: add reg cache data writing back path

Parameters: add parameters for reg cache

Backend fixtiming: fix rab/exuwb/wbtorob timing (#3032)

rab:
fix commit/walk/special walk Count from popcount to priority mux
exuwb:
fix exuwb Nto1 logic: add int/fp/vec 3 wbpath to wbarbite

Backend fixtiming: fix rab/exuwb/wbtorob timing (#3032)

rab:
fix commit/walk/special walk Count from popcount to priority mux
exuwb:
fix exuwb Nto1 logic: add int/fp/vec 3 wbpath to wbarbiter
wbtorob:
fix writebacknum count: delete extra count for exu which cannot be compressed

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FuConfig: split dataBits into destDataBits and srcDataBits for distinguish input and output data width

WbDataPath: support v0 & vl split

FuConfig: add writeV0Rf writeVlRf

DataPath: support v0 & vl split

Backend: update all Params' signals and methods for v0 & vl split

Backend: add some basic signals for v0 & vl split

Merge branch 'master' into vlsu-merge-master-0504

Backend: add FpScheduler

Merge branch 'master' into vlsu-tmp-master

rv64v: add ignore oldvd judgement in issue queue
1. when the instruction depend on old vd, we cannot set the srctype to imm
2. when vl = 0, we cannot set the srctype to imm because the vd keep the ol

rv64v: add ignore oldvd judgement in issue queue
1. when the instruction depend on old vd, we cannot set the srctype to imm
2. when vl = 0, we cannot set the srctype to imm because the vd keep the old value
3. when vl = vlmax, we can set srctype to imm when vta is not se

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Backend: support vector load&store better

* Todo: add more IQs for vector load&store
* Todo: make vector memory inst issue out of order
* Todo: fix bugs

rv64v: fix the logic of writing vtype for vsetvl instruction (#2875)

IssueQueue, BypassNetwork: add 1 cycle delay when writing back to vf regfile

Backend: vf instr add Og2 stage (#2810)

* Backend: vf instr add Og2 stage

* Update ExeUnitParams.scala

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Co-authored-by: zhanglyGit <[email protected]>

WbDataPath: add 1 cycle delay when vf exe units write back to int regfile