1package xiangshan.backend.exu 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import xiangshan.backend.BackendParams 7import xiangshan.backend.Bundles.{ExuBypassBundle, ExuInput, ExuOutput} 8import xiangshan.backend.datapath.DataConfig.DataConfig 9import xiangshan.backend.datapath.RdConfig._ 10import xiangshan.backend.datapath.WbConfig.{IntWB, PregWB, VfWB, FpWB} 11import xiangshan.backend.datapath.{DataConfig, WakeUpConfig} 12import xiangshan.backend.fu.{FuConfig, FuType} 13import xiangshan.backend.issue.{IssueBlockParams, SchedulerType, IntScheduler, VfScheduler, MemScheduler} 14import scala.collection.mutable 15 16case class ExeUnitParams( 17 name : String, 18 fuConfigs : Seq[FuConfig], 19 wbPortConfigs : Seq[PregWB], 20 rfrPortConfigs: Seq[Seq[RdConfig]], 21 copyWakeupOut: Boolean = false, 22 copyDistance: Int = 1, 23 fakeUnit : Boolean = false, 24)( 25 implicit 26 val schdType: SchedulerType, 27) { 28 // calculated configs 29 var iqWakeUpSourcePairs: Seq[WakeUpConfig] = Seq() 30 var iqWakeUpSinkPairs: Seq[WakeUpConfig] = Seq() 31 // used in bypass to select data of exu output 32 var exuIdx: Int = -1 33 var backendParam: BackendParams = null 34 35 val numIntSrc: Int = fuConfigs.map(_.numIntSrc).max 36 val numFpSrc: Int = fuConfigs.map(_.numFpSrc).max 37 val numVecSrc: Int = fuConfigs.map(_.numVecSrc).max 38 val numVfSrc: Int = fuConfigs.map(_.numVfSrc).max 39 val numRegSrc: Int = fuConfigs.map(_.numRegSrc).max 40 val numSrc: Int = fuConfigs.map(_.numSrc).max 41 val dataBitsMax: Int = fuConfigs.map(_.dataBits).max 42 val readIntRf: Boolean = numIntSrc > 0 43 val readFpRf: Boolean = numFpSrc > 0 44 val readVecRf: Boolean = numVecSrc > 0 45 val readVfRf: Boolean = numVfSrc > 0 46 val writeIntRf: Boolean = fuConfigs.map(_.writeIntRf).reduce(_ || _) 47 val writeFpRf: Boolean = fuConfigs.map(_.writeFpRf).reduce(_ || _) 48 val writeVecRf: Boolean = fuConfigs.map(_.writeVecRf).reduce(_ || _) 49 val needIntWen: Boolean = fuConfigs.map(_.needIntWen).reduce(_ || _) 50 val needFpWen: Boolean = fuConfigs.map(_.needFpWen).reduce(_ || _) 51 val needVecWen: Boolean = fuConfigs.map(_.needVecWen).reduce(_ || _) 52 val needOg2: Boolean = fuConfigs.map(_.needOg2).reduce(_ || _) 53 val writeVfRf: Boolean = writeVecRf 54 val writeFflags: Boolean = fuConfigs.map(_.writeFflags).reduce(_ || _) 55 val writeVxsat: Boolean = fuConfigs.map(_.writeVxsat).reduce(_ || _) 56 val hasNoDataWB: Boolean = fuConfigs.map(_.hasNoDataWB).reduce(_ && _) 57 val hasRedirect: Boolean = fuConfigs.map(_.hasRedirect).reduce(_ || _) 58 val hasPredecode: Boolean = fuConfigs.map(_.hasPredecode).reduce(_ || _) 59 val exceptionOut: Seq[Int] = fuConfigs.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted 60 val hasLoadError: Boolean = fuConfigs.map(_.hasLoadError).reduce(_ || _) 61 val flushPipe: Boolean = fuConfigs.map(_.flushPipe).reduce(_ || _) 62 val replayInst: Boolean = fuConfigs.map(_.replayInst).reduce(_ || _) 63 val trigger: Boolean = fuConfigs.map(_.trigger).reduce(_ || _) 64 val needExceptionGen: Boolean = exceptionOut.nonEmpty || flushPipe || replayInst || trigger 65 val needPc: Boolean = fuConfigs.map(_.needPc).reduce(_ || _) 66 val needTarget: Boolean = fuConfigs.map(_.needTargetPc).reduce(_ || _) 67 val needPdInfo: Boolean = fuConfigs.map(_.needPdInfo).reduce(_ || _) 68 val needSrcFrm: Boolean = fuConfigs.map(_.needSrcFrm).reduce(_ || _) 69 val needSrcVxrm: Boolean = fuConfigs.map(_.needSrcVxrm).reduce(_ || _) 70 val needFPUCtrl: Boolean = fuConfigs.map(_.needFPUCtrl).reduce(_ || _) 71 val needVPUCtrl: Boolean = fuConfigs.map(_.needVecCtrl).reduce(_ || _) 72 val writeVConfig: Boolean = fuConfigs.map(_.writeVConfig).reduce(_ || _) 73 val writeVType: Boolean = fuConfigs.map(_.writeVType).reduce(_ || _) 74 val isHighestWBPriority: Boolean = wbPortConfigs.forall(_.priority == 0) 75 76 val isIntExeUnit: Boolean = schdType.isInstanceOf[IntScheduler] 77 val isVfExeUnit: Boolean = schdType.isInstanceOf[VfScheduler] 78 val isMemExeUnit: Boolean = schdType.isInstanceOf[MemScheduler] 79 80 require(needPc && needTarget || !needPc && !needTarget, "The ExeUnit must need both PC and Target PC") 81 82 def copyNum: Int = { 83 val setIQ = mutable.Set[IssueBlockParams]() 84 iqWakeUpSourcePairs.map(_.sink).foreach{ wakeupSink => 85 backendParam.allIssueParams.map{ issueParams => 86 if (issueParams.exuBlockParams.contains(wakeupSink.getExuParam(backendParam.allExuParams))) { 87 setIQ.add(issueParams) 88 } 89 } 90 } 91 println(s"[Backend] exuIdx ${exuIdx} numWakeupIQ ${setIQ.size}") 92 1 + setIQ.size / copyDistance 93 } 94 def rdPregIdxWidth: Int = { 95 this.pregRdDataCfgSet.map(dataCfg => backendParam.getPregParams(dataCfg).addrWidth).fold(0)(_ max _) 96 } 97 98 def wbPregIdxWidth: Int = { 99 this.pregWbDataCfgSet.map(dataCfg => backendParam.getPregParams(dataCfg).addrWidth).fold(0)(_ max _) 100 } 101 102 val writeIntFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeIntRf) 103 val writeFpFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeFpRf) 104 val writeVfFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeVecRf) 105 106 /** 107 * Check if this exu has certain latency 108 */ 109 def latencyCertain: Boolean = fuConfigs.map(x => x.latency.latencyVal.nonEmpty).reduce(_ && _) 110 def intLatencyCertain: Boolean = writeIntFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 111 def fpLatencyCertain: Boolean = writeFpFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 112 def vfLatencyCertain: Boolean = writeVfFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 113 // only load use it 114 def hasUncertainLatencyVal: Boolean = fuConfigs.map(x => x.latency.uncertainLatencyVal.nonEmpty).reduce(_ || _) 115 116 /** 117 * Get mapping from FuType to Latency value. 118 * If both [[latencyCertain]] and [[hasUncertainLatencyVal]] are false, get empty [[Map]] 119 * 120 * @return Map[ [[BigInt]], Latency] 121 */ 122 def fuLatencyMap: Map[FuType.OHType, Int] = { 123 if (latencyCertain) 124 if(needOg2) fuConfigs.map(x => (x.fuType, x.latency.latencyVal.get + 1)).toMap else fuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 125 else if (hasUncertainLatencyVal) 126 fuConfigs.map(x => (x.fuType, x.latency.uncertainLatencyVal)).toMap.filter(_._2.nonEmpty).map(x => (x._1, x._2.get)) 127 else 128 Map() 129 } 130 def wakeUpFuLatencyMap: Map[FuType.OHType, Int] = { 131 if (latencyCertain) 132 fuConfigs.filterNot(_.hasNoDataWB).map(x => (x.fuType, x.latency.latencyVal.get)).toMap 133 else if (hasUncertainLatencyVal) 134 fuConfigs.filterNot(_.hasNoDataWB).map(x => (x.fuType, x.latency.uncertainLatencyVal.get)).toMap 135 else 136 Map() 137 } 138 139 /** 140 * Get set of latency of function units. 141 * If both [[latencyCertain]] and [[hasUncertainLatencyVal]] are false, get empty [[Set]] 142 * 143 * @return Set[Latency] 144 */ 145 def fuLatancySet: Set[Int] = fuLatencyMap.values.toSet 146 147 def wakeUpFuLatancySet: Set[Int] = wakeUpFuLatencyMap.values.toSet 148 149 def latencyValMax: Int = fuLatancySet.fold(0)(_ max _) 150 151 def intFuLatencyMap: Map[FuType.OHType, Int] = { 152 if (intLatencyCertain) { 153 if (isVfExeUnit) { 154 // vf exe unit writing back to int regfile should delay 1 cycle 155 // vf exe unit need og2 --> delay 1 cycle 156 writeIntFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get + 2)).toMap 157 } else { 158 writeIntFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 159 } 160 } 161 else 162 Map() 163 } 164 165 def intLatencyValMax: Int = intFuLatencyMap.values.fold(0)(_ max _) 166 167 def fpFuLatencyMap: Map[FuType.OHType, Int] = { 168 if (fpLatencyCertain) 169 writeFpFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 170 else 171 Map() 172 } 173 174 def fpLatencyValMax: Int = fpFuLatencyMap.values.fold(0)(_ max _) 175 176 def vfFuLatencyMap: Map[FuType.OHType, Int] = { 177 if (vfLatencyCertain) 178 if(needOg2) writeVfFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get + 1)).toMap else writeVfFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 179 else 180 Map() 181 } 182 183 def vfLatencyValMax: Int = vfFuLatencyMap.values.fold(0)(_ max _) 184 185 /** 186 * Check if this exu has fixed latency 187 */ 188 def isFixedLatency: Boolean = { 189 if (latencyCertain) 190 return fuConfigs.map(x => x.latency.latencyVal.get == fuConfigs.head.latency.latencyVal.get).reduce(_ && _) 191 false 192 } 193 194 def hasCSR: Boolean = fuConfigs.map(_.isCsr).reduce(_ || _) 195 196 def hasFence: Boolean = fuConfigs.map(_.isFence).reduce(_ || _) 197 198 def hasBrhFu = fuConfigs.map(_.fuType == FuType.brh).reduce(_ || _) 199 200 def hasJmpFu = fuConfigs.map(_.fuType == FuType.jmp).reduce(_ || _) 201 202 def hasLoadFu = fuConfigs.map(_.name == "ldu").reduce(_ || _) 203 204 def hasVLoadFu = fuConfigs.map(_.fuType == FuType.vldu).reduce(_ || _) 205 206 def hasVStoreFu = fuConfigs.map(_.fuType == FuType.vstu).reduce(_ || _) 207 208 def hasVecLsFu = fuConfigs.map(x => FuType.FuTypeOrR(x.fuType, Seq(FuType.vldu, FuType.vstu))).reduce(_ || _) 209 210 def hasStoreAddrFu = fuConfigs.map(_.name == "sta").reduce(_ || _) 211 212 def hasStdFu = fuConfigs.map(_.name == "std").reduce(_ || _) 213 214 def hasMemAddrFu = hasLoadFu || hasStoreAddrFu || hasVLoadFu || hasHyldaFu || hasHystaFu || hasVLoadFu || hasVStoreFu 215 216 def hasHyldaFu = fuConfigs.map(_.name == "hylda").reduce(_ || _) 217 218 def hasHystaFu = fuConfigs.map(_.name == "hysta").reduce(_ || _) 219 220 def hasLoadExu = hasLoadFu || hasHyldaFu 221 222 def hasStoreAddrExu = hasStoreAddrFu || hasHystaFu 223 224 def hasVecFu = fuConfigs.map(x => FuConfig.VecArithFuConfigs.contains(x)).reduce(_ || _) 225 226 def getSrcDataType(srcIdx: Int): Set[DataConfig] = { 227 fuConfigs.map(_.getSrcDataType(srcIdx)).reduce(_ ++ _) 228 } 229 230 def immType: Set[UInt] = fuConfigs.map(x => x.immType).reduce(_ ++ _) 231 232 def getWBSource: SchedulerType = { 233 schdType 234 } 235 236 def hasCrossWb: Boolean = { 237 schdType match { 238 case IntScheduler() => writeFpRf || writeVecRf 239 case VfScheduler() => writeIntRf 240 case _ => false 241 } 242 } 243 244 def canAccept(fuType: UInt): Bool = { 245 Cat(fuConfigs.map(_.fuType.U === fuType)).orR 246 } 247 248 def hasUncertainLatency: Boolean = fuConfigs.map(_.latency.latencyVal.isEmpty).reduce(_ || _) 249 250 def bindBackendParam(param: BackendParams): Unit = { 251 backendParam = param 252 } 253 254 def updateIQWakeUpConfigs(cfgs: Seq[WakeUpConfig]) = { 255 this.iqWakeUpSourcePairs = cfgs.filter(_.source.name == this.name) 256 this.iqWakeUpSinkPairs = cfgs.filter(_.sink.name == this.name) 257 if (this.isIQWakeUpSource) { 258 require(!this.hasUncertainLatency || hasLoadFu || hasHyldaFu, s"${this.name} is a not-LDU IQ wake up source , but has UncertainLatency") 259 } 260 } 261 262 def updateExuIdx(idx: Int): Unit = { 263 this.exuIdx = idx 264 } 265 266 def isIQWakeUpSource = this.iqWakeUpSourcePairs.nonEmpty 267 268 def isIQWakeUpSink = this.iqWakeUpSinkPairs.nonEmpty 269 270 def getIntWBPort = { 271 wbPortConfigs.collectFirst { 272 case x: IntWB => x 273 } 274 } 275 276 def getFpWBPort = { 277 wbPortConfigs.collectFirst { 278 case x: FpWB => x 279 } 280 } 281 282 def getVfWBPort = { 283 wbPortConfigs.collectFirst { 284 case x: VfWB => x 285 } 286 } 287 288 /** 289 * Get the [[DataConfig]] that this exu need to read 290 */ 291 def pregRdDataCfgSet: Set[DataConfig] = { 292 this.rfrPortConfigs.flatten.map(_.getDataConfig).toSet 293 } 294 295 /** 296 * Get the [[DataConfig]] that this exu need to write 297 */ 298 def pregWbDataCfgSet: Set[DataConfig] = { 299 this.wbPortConfigs.map(_.dataCfg).toSet 300 } 301 302 def getRfReadDataCfgSet: Seq[Set[DataConfig]] = { 303 val fuSrcsCfgSet: Seq[Seq[Set[DataConfig]]] = fuConfigs.map(_.getRfReadDataCfgSet) 304 val alignedFuSrcsCfgSet: Seq[Seq[Set[DataConfig]]] = fuSrcsCfgSet.map(x => x ++ Seq.fill(numRegSrc - x.length)(Set[DataConfig]())) 305 306 val exuSrcsCfgSet = alignedFuSrcsCfgSet.reduce((x, y) => (x zip y).map { case (cfg1, cfg2) => cfg1 union cfg2 }) 307 308 exuSrcsCfgSet 309 } 310 311 /** 312 * Get the [[DataConfig]] mapped indices of source data of exu 313 * 314 * @example 315 * {{{ 316 * fuCfg.srcData = Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()) 317 * getRfReadSrcIdx(VecData()) = Seq(0, 1, 2) 318 * getRfReadSrcIdx(MaskSrcData()) = Seq(3) 319 * getRfReadSrcIdx(VConfigData()) = Seq(4) 320 * }}} 321 * @return Map[DataConfig -> Seq[indices]] 322 */ 323 def getRfReadSrcIdx: Map[DataConfig, Seq[Int]] = { 324 val dataCfgs = DataConfig.RegSrcDataSet 325 val rfRdDataCfgSet = this.getRfReadDataCfgSet 326 dataCfgs.toSeq.map { cfg => 327 ( 328 cfg, 329 rfRdDataCfgSet.zipWithIndex.map { case (set, srcIdx) => 330 if (set.contains(cfg)) 331 Option(srcIdx) 332 else 333 None 334 }.filter(_.nonEmpty).map(_.get) 335 ) 336 }.toMap 337 } 338 339 def genExuModule(implicit p: Parameters): ExeUnit = { 340 new ExeUnit(this) 341 } 342 343 def genExuInputBundle(implicit p: Parameters): ExuInput = { 344 new ExuInput(this) 345 } 346 347 def genExuOutputBundle(implicit p: Parameters): ExuOutput = { 348 new ExuOutput(this) 349 } 350 351 def genExuBypassBundle(implicit p: Parameters): ExuBypassBundle = { 352 new ExuBypassBundle(this) 353 } 354} 355