1package xiangshan.backend.exu 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import xiangshan.backend.BackendParams 7import xiangshan.backend.Bundles.{ExuBypassBundle, ExuInput, ExuOutput} 8import xiangshan.backend.datapath.DataConfig.DataConfig 9import xiangshan.backend.datapath.RdConfig._ 10import xiangshan.backend.datapath.WbConfig.{IntWB, PregWB, VfWB} 11import xiangshan.backend.datapath.{DataConfig, WakeUpConfig} 12import xiangshan.backend.fu.{FuConfig, FuType} 13import xiangshan.backend.issue.{IssueBlockParams, SchedulerType, IntScheduler, VfScheduler, MemScheduler} 14import scala.collection.mutable 15 16case class ExeUnitParams( 17 name : String, 18 fuConfigs : Seq[FuConfig], 19 wbPortConfigs : Seq[PregWB], 20 rfrPortConfigs: Seq[Seq[RdConfig]], 21 copyWakeupOut: Boolean = false, 22 copyDistance: Int = 1, 23 fakeUnit : Boolean = false, 24)( 25 implicit 26 val schdType: SchedulerType, 27) { 28 // calculated configs 29 var iqWakeUpSourcePairs: Seq[WakeUpConfig] = Seq() 30 var iqWakeUpSinkPairs: Seq[WakeUpConfig] = Seq() 31 // used in bypass to select data of exu output 32 var exuIdx: Int = -1 33 var backendParam: BackendParams = null 34 35 val numIntSrc: Int = fuConfigs.map(_.numIntSrc).max 36 val numFpSrc: Int = fuConfigs.map(_.numFpSrc).max 37 val numVecSrc: Int = fuConfigs.map(_.numVecSrc).max 38 val numVfSrc: Int = fuConfigs.map(_.numVfSrc).max 39 val numRegSrc: Int = fuConfigs.map(_.numRegSrc).max 40 val numSrc: Int = fuConfigs.map(_.numSrc).max 41 val dataBitsMax: Int = fuConfigs.map(_.dataBits).max 42 val readIntRf: Boolean = numIntSrc > 0 43 val readFpRf: Boolean = numFpSrc > 0 44 val readVecRf: Boolean = numVecSrc > 0 45 val writeIntRf: Boolean = fuConfigs.map(_.writeIntRf).reduce(_ || _) 46 val writeFpRf: Boolean = fuConfigs.map(_.writeFpRf).reduce(_ || _) 47 val writeVecRf: Boolean = fuConfigs.map(_.writeVecRf).reduce(_ || _) 48 val needIntWen: Boolean = fuConfigs.map(_.needIntWen).reduce(_ || _) 49 val needFpWen: Boolean = fuConfigs.map(_.needFpWen).reduce(_ || _) 50 val needVecWen: Boolean = fuConfigs.map(_.needVecWen).reduce(_ || _) 51 val writeVfRf: Boolean = writeFpRf || writeVecRf 52 val writeFflags: Boolean = fuConfigs.map(_.writeFflags).reduce(_ || _) 53 val writeVxsat: Boolean = fuConfigs.map(_.writeVxsat).reduce(_ || _) 54 val hasNoDataWB: Boolean = fuConfigs.map(_.hasNoDataWB).reduce(_ && _) 55 val hasRedirect: Boolean = fuConfigs.map(_.hasRedirect).reduce(_ || _) 56 val hasPredecode: Boolean = fuConfigs.map(_.hasPredecode).reduce(_ || _) 57 val exceptionOut: Seq[Int] = fuConfigs.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted 58 val hasLoadError: Boolean = fuConfigs.map(_.hasLoadError).reduce(_ || _) 59 val flushPipe: Boolean = fuConfigs.map(_.flushPipe).reduce(_ || _) 60 val replayInst: Boolean = fuConfigs.map(_.replayInst).reduce(_ || _) 61 val trigger: Boolean = fuConfigs.map(_.trigger).reduce(_ || _) 62 val needExceptionGen: Boolean = exceptionOut.nonEmpty || flushPipe || replayInst || trigger 63 val needPc: Boolean = fuConfigs.map(_.needPc).reduce(_ || _) 64 val needTarget: Boolean = fuConfigs.map(_.needTargetPc).reduce(_ || _) 65 val needPdInfo: Boolean = fuConfigs.map(_.needPdInfo).reduce(_ || _) 66 val needSrcFrm: Boolean = fuConfigs.map(_.needSrcFrm).reduce(_ || _) 67 val needSrcVxrm: Boolean = fuConfigs.map(_.needSrcVxrm).reduce(_ || _) 68 val needFPUCtrl: Boolean = fuConfigs.map(_.needFPUCtrl).reduce(_ || _) 69 val needVPUCtrl: Boolean = fuConfigs.map(_.needVecCtrl).reduce(_ || _) 70 val isHighestWBPriority: Boolean = wbPortConfigs.forall(_.priority == 0) 71 72 val isIntExeUnit: Boolean = schdType.isInstanceOf[IntScheduler] 73 val isVfExeUnit: Boolean = schdType.isInstanceOf[VfScheduler] 74 val isMemExeUnit: Boolean = schdType.isInstanceOf[MemScheduler] 75 76 require(needPc && needTarget || !needPc && !needTarget, "The ExeUnit must need both PC and Target PC") 77 78 def copyNum: Int = { 79 val setIQ = mutable.Set[IssueBlockParams]() 80 iqWakeUpSourcePairs.map(_.sink).foreach{ wakeupSink => 81 backendParam.allIssueParams.map{ issueParams => 82 if (issueParams.exuBlockParams.contains(wakeupSink.getExuParam(backendParam.allExuParams))) { 83 setIQ.add(issueParams) 84 } 85 } 86 } 87 println(s"[Backend] exuIdx ${exuIdx} numWakeupIQ ${setIQ.size}") 88 1 + setIQ.size / copyDistance 89 } 90 def rdPregIdxWidth: Int = { 91 this.pregRdDataCfgSet.map(dataCfg => backendParam.getPregParams(dataCfg).addrWidth).fold(0)(_ max _) 92 } 93 94 def wbPregIdxWidth: Int = { 95 this.pregWbDataCfgSet.map(dataCfg => backendParam.getPregParams(dataCfg).addrWidth).fold(0)(_ max _) 96 } 97 98 val writeIntFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeIntRf) 99 val writeVfFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeFpRf || x.writeVecRf) 100 101 /** 102 * Check if this exu has certain latency 103 */ 104 def latencyCertain: Boolean = fuConfigs.map(x => x.latency.latencyVal.nonEmpty).reduce(_ && _) 105 def intLatencyCertain: Boolean = writeIntFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 106 def vfLatencyCertain: Boolean = writeVfFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 107 // only load use it 108 def hasUncertainLatencyVal: Boolean = fuConfigs.map(x => x.latency.uncertainLatencyVal.nonEmpty).reduce(_ || _) 109 110 /** 111 * Get mapping from FuType to Latency value. 112 * If both [[latencyCertain]] and [[hasUncertainLatencyVal]] are false, get empty [[Map]] 113 * 114 * @return Map[ [[BigInt]], Latency] 115 */ 116 def fuLatencyMap: Map[FuType.OHType, Int] = { 117 if (latencyCertain) 118 fuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 119 else if (hasUncertainLatencyVal) 120 fuConfigs.map(x => (x.fuType, x.latency.uncertainLatencyVal)).toMap.filter(_._2.nonEmpty).map(x => (x._1, x._2.get)) 121 else 122 Map() 123 } 124 def wakeUpFuLatencyMap: Map[FuType.OHType, Int] = { 125 if (latencyCertain) 126 fuConfigs.filterNot(_.hasNoDataWB).map(x => (x.fuType, x.latency.latencyVal.get)).toMap 127 else if (hasUncertainLatencyVal) 128 fuConfigs.filterNot(_.hasNoDataWB).map(x => (x.fuType, x.latency.uncertainLatencyVal.get)).toMap 129 else 130 Map() 131 } 132 133 /** 134 * Get set of latency of function units. 135 * If both [[latencyCertain]] and [[hasUncertainLatencyVal]] are false, get empty [[Set]] 136 * 137 * @return Set[Latency] 138 */ 139 def fuLatancySet: Set[Int] = fuLatencyMap.values.toSet 140 141 def wakeUpFuLatancySet: Set[Int] = wakeUpFuLatencyMap.values.toSet 142 143 def latencyValMax: Int = fuLatancySet.fold(0)(_ max _) 144 145 def intFuLatencyMap: Map[FuType.OHType, Int] = { 146 if (intLatencyCertain) { 147 if (isVfExeUnit) { 148 // vf exe unit writing back to int regfile should delay 1 cycle 149 writeIntFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get + 1)).toMap 150 } else { 151 writeIntFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 152 } 153 } 154 else 155 Map() 156 } 157 158 def intLatencyValMax: Int = intFuLatencyMap.values.fold(0)(_ max _) 159 160 def vfFuLatencyMap: Map[FuType.OHType, Int] = { 161 if (vfLatencyCertain) 162 writeVfFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 163 else 164 Map() 165 } 166 167 def vfLatencyValMax: Int = vfFuLatencyMap.values.fold(0)(_ max _) 168 169 /** 170 * Check if this exu has fixed latency 171 */ 172 def isFixedLatency: Boolean = { 173 if (latencyCertain) 174 return fuConfigs.map(x => x.latency.latencyVal.get == fuConfigs.head.latency.latencyVal.get).reduce(_ && _) 175 false 176 } 177 178 def hasCSR: Boolean = fuConfigs.map(_.isCsr).reduce(_ || _) 179 180 def hasFence: Boolean = fuConfigs.map(_.isFence).reduce(_ || _) 181 182 def hasBrhFu = fuConfigs.map(_.fuType == FuType.brh).reduce(_ || _) 183 184 def hasJmpFu = fuConfigs.map(_.fuType == FuType.jmp).reduce(_ || _) 185 186 def hasLoadFu = fuConfigs.map(_.name == "ldu").reduce(_ || _) 187 188 def hasVLoadFu = fuConfigs.map(_.fuType == FuType.vldu).reduce(_ || _) 189 190 def hasVStoreFu = fuConfigs.map(_.fuType == FuType.vstu).reduce(_ || _) 191 192 def hasVecLsFu = fuConfigs.map(x => FuType.FuTypeOrR(x.fuType, Seq(FuType.vldu, FuType.vstu))).reduce(_ || _) 193 194 def hasStoreAddrFu = fuConfigs.map(_.name == "sta").reduce(_ || _) 195 196 def hasStdFu = fuConfigs.map(_.name == "std").reduce(_ || _) 197 198 def hasMemAddrFu = hasLoadFu || hasStoreAddrFu || hasVLoadFu || hasHyldaFu || hasHystaFu || hasVLoadFu || hasVStoreFu 199 200 def hasHyldaFu = fuConfigs.map(_.name == "hylda").reduce(_ || _) 201 202 def hasHystaFu = fuConfigs.map(_.name == "hysta").reduce(_ || _) 203 204 def hasLoadExu = hasLoadFu || hasHyldaFu 205 206 def hasStoreAddrExu = hasStoreAddrFu || hasHystaFu 207 208 def hasVecFu = fuConfigs.map(x => FuConfig.VecArithFuConfigs.contains(x)).reduce(_ || _) 209 210 def getSrcDataType(srcIdx: Int): Set[DataConfig] = { 211 fuConfigs.map(_.getSrcDataType(srcIdx)).reduce(_ ++ _) 212 } 213 214 def immType: Set[UInt] = fuConfigs.map(x => x.immType).reduce(_ ++ _) 215 216 def getWBSource: SchedulerType = { 217 schdType 218 } 219 220 def hasCrossWb: Boolean = { 221 schdType match { 222 case IntScheduler() => writeFpRf || writeVecRf 223 case VfScheduler() => writeIntRf 224 case _ => false 225 } 226 } 227 228 def canAccept(fuType: UInt): Bool = { 229 Cat(fuConfigs.map(_.fuType.U === fuType)).orR 230 } 231 232 def hasUncertainLatency: Boolean = fuConfigs.map(_.latency.latencyVal.isEmpty).reduce(_ || _) 233 234 def bindBackendParam(param: BackendParams): Unit = { 235 backendParam = param 236 } 237 238 def updateIQWakeUpConfigs(cfgs: Seq[WakeUpConfig]) = { 239 this.iqWakeUpSourcePairs = cfgs.filter(_.source.name == this.name) 240 this.iqWakeUpSinkPairs = cfgs.filter(_.sink.name == this.name) 241 if (this.isIQWakeUpSource) { 242 require(!this.hasUncertainLatency || hasLoadFu || hasHyldaFu, s"${this.name} is a not-LDU IQ wake up source , but has UncertainLatency") 243 } 244 } 245 246 def updateExuIdx(idx: Int): Unit = { 247 this.exuIdx = idx 248 } 249 250 def isIQWakeUpSource = this.iqWakeUpSourcePairs.nonEmpty 251 252 def isIQWakeUpSink = this.iqWakeUpSinkPairs.nonEmpty 253 254 def getIntWBPort = { 255 wbPortConfigs.collectFirst { 256 case x: IntWB => x 257 } 258 } 259 260 def getVfWBPort = { 261 wbPortConfigs.collectFirst { 262 case x: VfWB => x 263 } 264 } 265 266 /** 267 * Get the [[DataConfig]] that this exu need to read 268 */ 269 def pregRdDataCfgSet: Set[DataConfig] = { 270 this.rfrPortConfigs.flatten.map(_.getDataConfig).toSet 271 } 272 273 /** 274 * Get the [[DataConfig]] that this exu need to write 275 */ 276 def pregWbDataCfgSet: Set[DataConfig] = { 277 this.wbPortConfigs.map(_.dataCfg).toSet 278 } 279 280 def getRfReadDataCfgSet: Seq[Set[DataConfig]] = { 281 val fuSrcsCfgSet: Seq[Seq[Set[DataConfig]]] = fuConfigs.map(_.getRfReadDataCfgSet) 282 val alignedFuSrcsCfgSet: Seq[Seq[Set[DataConfig]]] = fuSrcsCfgSet.map(x => x ++ Seq.fill(numRegSrc - x.length)(Set[DataConfig]())) 283 284 val exuSrcsCfgSet = alignedFuSrcsCfgSet.reduce((x, y) => (x zip y).map { case (cfg1, cfg2) => cfg1 union cfg2 }) 285 286 exuSrcsCfgSet 287 } 288 289 /** 290 * Get the [[DataConfig]] mapped indices of source data of exu 291 * 292 * @example 293 * {{{ 294 * fuCfg.srcData = Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()) 295 * getRfReadSrcIdx(VecData()) = Seq(0, 1, 2) 296 * getRfReadSrcIdx(MaskSrcData()) = Seq(3) 297 * getRfReadSrcIdx(VConfigData()) = Seq(4) 298 * }}} 299 * @return Map[DataConfig -> Seq[indices]] 300 */ 301 def getRfReadSrcIdx: Map[DataConfig, Seq[Int]] = { 302 val dataCfgs = DataConfig.RegSrcDataSet 303 val rfRdDataCfgSet = this.getRfReadDataCfgSet 304 dataCfgs.toSeq.map { cfg => 305 ( 306 cfg, 307 rfRdDataCfgSet.zipWithIndex.map { case (set, srcIdx) => 308 if (set.contains(cfg)) 309 Option(srcIdx) 310 else 311 None 312 }.filter(_.nonEmpty).map(_.get) 313 ) 314 }.toMap 315 } 316 317 def genExuModule(implicit p: Parameters): ExeUnit = { 318 new ExeUnit(this) 319 } 320 321 def genExuInputBundle(implicit p: Parameters): ExuInput = { 322 new ExuInput(this) 323 } 324 325 def genExuOutputBundle(implicit p: Parameters): ExuOutput = { 326 new ExuOutput(this) 327 } 328 329 def genExuBypassBundle(implicit p: Parameters): ExuBypassBundle = { 330 new ExuBypassBundle(this) 331 } 332} 333