1package xiangshan.backend.exu 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import xiangshan.backend.BackendParams 7import xiangshan.backend.Bundles.{ExuBypassBundle, ExuInput, ExuOutput} 8import xiangshan.backend.datapath.DataConfig.DataConfig 9import xiangshan.backend.datapath.RdConfig._ 10import xiangshan.backend.datapath.WbConfig._ 11import xiangshan.backend.datapath.{DataConfig, WakeUpConfig} 12import xiangshan.backend.fu.{FuConfig, FuType} 13import xiangshan.backend.issue.{IssueBlockParams, SchedulerType, IntScheduler, VfScheduler, MemScheduler} 14import scala.collection.mutable 15 16case class ExeUnitParams( 17 name : String, 18 fuConfigs : Seq[FuConfig], 19 wbPortConfigs : Seq[PregWB], 20 rfrPortConfigs: Seq[Seq[RdConfig]], 21 copyWakeupOut: Boolean = false, 22 copyDistance: Int = 1, 23 fakeUnit : Boolean = false, 24)( 25 implicit 26 val schdType: SchedulerType, 27) { 28 // calculated configs 29 var iqWakeUpSourcePairs: Seq[WakeUpConfig] = Seq() 30 var iqWakeUpSinkPairs: Seq[WakeUpConfig] = Seq() 31 // used in bypass to select data of exu output 32 var exuIdx: Int = -1 33 var backendParam: BackendParams = null 34 35 val numIntSrc: Int = fuConfigs.map(_.numIntSrc).max 36 val numFpSrc: Int = fuConfigs.map(_.numFpSrc).max 37 val numVecSrc: Int = fuConfigs.map(_.numVecSrc).max 38 val numVfSrc: Int = fuConfigs.map(_.numVfSrc).max 39 val numV0Src: Int = fuConfigs.map(_.numV0Src).max 40 val numVlSrc: Int = fuConfigs.map(_.numVlSrc).max 41 val numRegSrc: Int = fuConfigs.map(_.numRegSrc).max 42 val numSrc: Int = fuConfigs.map(_.numSrc).max 43 val destDataBitsMax: Int = fuConfigs.map(_.destDataBits).max 44 val srcDataBitsMax: Int = fuConfigs.map(x => x.srcDataBits.getOrElse(x.destDataBits)).max 45 val readIntRf: Boolean = numIntSrc > 0 46 val readFpRf: Boolean = numFpSrc > 0 47 val readVecRf: Boolean = numVecSrc > 0 48 val readVfRf: Boolean = numVfSrc > 0 49 val writeIntRf: Boolean = fuConfigs.map(_.writeIntRf).reduce(_ || _) 50 val writeFpRf: Boolean = fuConfigs.map(_.writeFpRf).reduce(_ || _) 51 val writeVecRf: Boolean = fuConfigs.map(_.writeVecRf).reduce(_ || _) 52 val writeV0Rf: Boolean = fuConfigs.map(_.writeV0Rf).reduce(_ || _) 53 val writeVlRf: Boolean = fuConfigs.map(_.writeVlRf).reduce(_ || _) 54 val needIntWen: Boolean = fuConfigs.map(_.needIntWen).reduce(_ || _) 55 val needFpWen: Boolean = fuConfigs.map(_.needFpWen).reduce(_ || _) 56 val needVecWen: Boolean = fuConfigs.map(_.needVecWen).reduce(_ || _) 57 val needV0Wen: Boolean = fuConfigs.map(_.needV0Wen).reduce(_ || _) 58 val needVlWen: Boolean = fuConfigs.map(_.needVlWen).reduce(_ || _) 59 val needOg2: Boolean = fuConfigs.map(_.needOg2).reduce(_ || _) 60 val writeVfRf: Boolean = writeVecRf 61 val writeFflags: Boolean = fuConfigs.map(_.writeFflags).reduce(_ || _) 62 val writeVxsat: Boolean = fuConfigs.map(_.writeVxsat).reduce(_ || _) 63 val hasNoDataWB: Boolean = fuConfigs.map(_.hasNoDataWB).reduce(_ && _) 64 val hasRedirect: Boolean = fuConfigs.map(_.hasRedirect).reduce(_ || _) 65 val hasPredecode: Boolean = fuConfigs.map(_.hasPredecode).reduce(_ || _) 66 val exceptionOut: Seq[Int] = fuConfigs.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted 67 val hasLoadError: Boolean = fuConfigs.map(_.hasLoadError).reduce(_ || _) 68 val flushPipe: Boolean = fuConfigs.map(_.flushPipe).reduce(_ || _) 69 val replayInst: Boolean = fuConfigs.map(_.replayInst).reduce(_ || _) 70 val trigger: Boolean = fuConfigs.map(_.trigger).reduce(_ || _) 71 val needExceptionGen: Boolean = exceptionOut.nonEmpty || flushPipe || replayInst || trigger 72 val needPc: Boolean = fuConfigs.map(_.needPc).reduce(_ || _) 73 val needTarget: Boolean = fuConfigs.map(_.needTargetPc).reduce(_ || _) 74 val needPdInfo: Boolean = fuConfigs.map(_.needPdInfo).reduce(_ || _) 75 val needSrcFrm: Boolean = fuConfigs.map(_.needSrcFrm).reduce(_ || _) 76 val needSrcVxrm: Boolean = fuConfigs.map(_.needSrcVxrm).reduce(_ || _) 77 val needFPUCtrl: Boolean = fuConfigs.map(_.needFPUCtrl).reduce(_ || _) 78 val needVPUCtrl: Boolean = fuConfigs.map(_.needVecCtrl).reduce(_ || _) 79 val writeVConfig: Boolean = fuConfigs.map(_.writeVlRf).reduce(_ || _) 80 val writeVType: Boolean = fuConfigs.map(_.writeVType).reduce(_ || _) 81 val isHighestWBPriority: Boolean = wbPortConfigs.forall(_.priority == 0) 82 83 val isIntExeUnit: Boolean = schdType.isInstanceOf[IntScheduler] 84 val isVfExeUnit: Boolean = schdType.isInstanceOf[VfScheduler] 85 val isMemExeUnit: Boolean = schdType.isInstanceOf[MemScheduler] 86 87 require(needPc && needTarget || !needPc && !needTarget, "The ExeUnit must need both PC and Target PC") 88 89 def copyNum: Int = { 90 val setIQ = mutable.Set[IssueBlockParams]() 91 iqWakeUpSourcePairs.map(_.sink).foreach{ wakeupSink => 92 backendParam.allIssueParams.map{ issueParams => 93 if (issueParams.exuBlockParams.contains(wakeupSink.getExuParam(backendParam.allExuParams))) { 94 setIQ.add(issueParams) 95 } 96 } 97 } 98 println(s"[Backend] exuIdx ${exuIdx} numWakeupIQ ${setIQ.size}") 99 1 + setIQ.size / copyDistance 100 } 101 def rdPregIdxWidth: Int = { 102 this.pregRdDataCfgSet.map(dataCfg => backendParam.getPregParams(dataCfg).addrWidth).fold(0)(_ max _) 103 } 104 105 def wbPregIdxWidth: Int = { 106 this.pregWbDataCfgSet.map(dataCfg => backendParam.getPregParams(dataCfg).addrWidth).fold(0)(_ max _) 107 } 108 109 val writeIntFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeIntRf) 110 val writeFpFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeFpRf) 111 val writeVfFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeVecRf) 112 val writeV0FuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeV0Rf) 113 val writeVlFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeVlRf) 114 115 /** 116 * Check if this exu has certain latency 117 */ 118 def latencyCertain: Boolean = fuConfigs.map(x => x.latency.latencyVal.nonEmpty).reduce(_ && _) 119 def intLatencyCertain: Boolean = writeIntFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 120 def fpLatencyCertain: Boolean = writeFpFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 121 def vfLatencyCertain: Boolean = writeVfFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 122 def v0LatencyCertain: Boolean = writeV0FuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 123 def vlLatencyCertain: Boolean = writeVlFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 124 // only load use it 125 def hasUncertainLatencyVal: Boolean = fuConfigs.map(x => x.latency.uncertainLatencyVal.nonEmpty).reduce(_ || _) 126 127 /** 128 * Get mapping from FuType to Latency value. 129 * If both [[latencyCertain]] and [[hasUncertainLatencyVal]] are false, get empty [[Map]] 130 * 131 * @return Map[ [[BigInt]], Latency] 132 */ 133 def fuLatencyMap: Map[FuType.OHType, Int] = { 134 if (latencyCertain) 135 if(needOg2) fuConfigs.map(x => (x.fuType, x.latency.latencyVal.get + 1)).toMap else fuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 136 else if (hasUncertainLatencyVal) 137 fuConfigs.map(x => (x.fuType, x.latency.uncertainLatencyVal)).toMap.filter(_._2.nonEmpty).map(x => (x._1, x._2.get)) 138 else 139 Map() 140 } 141 def wakeUpFuLatencyMap: Map[FuType.OHType, Int] = { 142 if (latencyCertain) 143 fuConfigs.filterNot(_.hasNoDataWB).map(x => (x.fuType, x.latency.latencyVal.get)).toMap 144 else if (hasUncertainLatencyVal) 145 fuConfigs.filterNot(_.hasNoDataWB).map(x => (x.fuType, x.latency.uncertainLatencyVal.get)).toMap 146 else 147 Map() 148 } 149 150 /** 151 * Get set of latency of function units. 152 * If both [[latencyCertain]] and [[hasUncertainLatencyVal]] are false, get empty [[Set]] 153 * 154 * @return Set[Latency] 155 */ 156 def fuLatancySet: Set[Int] = fuLatencyMap.values.toSet 157 158 def wakeUpFuLatancySet: Set[Int] = wakeUpFuLatencyMap.values.toSet 159 160 def latencyValMax: Int = fuLatancySet.fold(0)(_ max _) 161 162 def intFuLatencyMap: Map[FuType.OHType, Int] = { 163 if (intLatencyCertain) { 164 if (isVfExeUnit) { 165 // vf exe unit writing back to int regfile should delay 1 cycle 166 // vf exe unit need og2 --> delay 1 cycle 167 writeIntFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get + 2)).toMap 168 } else { 169 writeIntFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 170 } 171 } 172 else 173 Map() 174 } 175 176 def intLatencyValMax: Int = intFuLatencyMap.values.fold(0)(_ max _) 177 178 def fpFuLatencyMap: Map[FuType.OHType, Int] = { 179 if (fpLatencyCertain) 180 writeFpFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 181 else 182 Map() 183 } 184 185 def fpLatencyValMax: Int = fpFuLatencyMap.values.fold(0)(_ max _) 186 187 def vfFuLatencyMap: Map[FuType.OHType, Int] = { 188 if (vfLatencyCertain) 189 if(needOg2) writeVfFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get + 1)).toMap else writeVfFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 190 else 191 Map() 192 } 193 194 def vfLatencyValMax: Int = vfFuLatencyMap.values.fold(0)(_ max _) 195 196 def v0FuLatencyMap: Map[FuType.OHType, Int] = { 197 if (v0LatencyCertain) 198 if(needOg2) writeV0FuConfigs.map(x => (x.fuType, x.latency.latencyVal.get + 1)).toMap else writeV0FuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 199 else 200 Map() 201 } 202 203 def v0LatencyValMax: Int = v0FuLatencyMap.values.fold(0)(_ max _) 204 205 def vlFuLatencyMap: Map[FuType.OHType, Int] = { 206 if (vlLatencyCertain) 207 if(needOg2) writeVlFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get + 1)).toMap else writeVlFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 208 else 209 Map() 210 } 211 212 def vlLatencyValMax: Int = vlFuLatencyMap.values.fold(0)(_ max _) 213 214 /** 215 * Check if this exu has fixed latency 216 */ 217 def isFixedLatency: Boolean = { 218 if (latencyCertain) 219 return fuConfigs.map(x => x.latency.latencyVal.get == fuConfigs.head.latency.latencyVal.get).reduce(_ && _) 220 false 221 } 222 223 def hasCSR: Boolean = fuConfigs.map(_.isCsr).reduce(_ || _) 224 225 def hasFence: Boolean = fuConfigs.map(_.isFence).reduce(_ || _) 226 227 def hasBrhFu = fuConfigs.map(_.fuType == FuType.brh).reduce(_ || _) 228 229 def hasJmpFu = fuConfigs.map(_.fuType == FuType.jmp).reduce(_ || _) 230 231 def hasLoadFu = fuConfigs.map(_.name == "ldu").reduce(_ || _) 232 233 def hasVLoadFu = fuConfigs.map(_.fuType == FuType.vldu).reduce(_ || _) 234 235 def hasVStoreFu = fuConfigs.map(_.fuType == FuType.vstu).reduce(_ || _) 236 237 def hasVecLsFu = fuConfigs.map(x => FuType.FuTypeOrR(x.fuType, Seq(FuType.vldu, FuType.vstu))).reduce(_ || _) 238 239 def hasStoreAddrFu = fuConfigs.map(_.name == "sta").reduce(_ || _) 240 241 def hasStdFu = fuConfigs.map(_.name == "std").reduce(_ || _) 242 243 def hasMemAddrFu = hasLoadFu || hasStoreAddrFu || hasVLoadFu || hasHyldaFu || hasHystaFu || hasVLoadFu || hasVStoreFu 244 245 def hasHyldaFu = fuConfigs.map(_.name == "hylda").reduce(_ || _) 246 247 def hasHystaFu = fuConfigs.map(_.name == "hysta").reduce(_ || _) 248 249 def hasLoadExu = hasLoadFu || hasHyldaFu 250 251 def hasStoreAddrExu = hasStoreAddrFu || hasHystaFu 252 253 def hasVecFu = fuConfigs.map(x => FuConfig.VecArithFuConfigs.contains(x)).reduce(_ || _) 254 255 def getSrcDataType(srcIdx: Int): Set[DataConfig] = { 256 fuConfigs.map(_.getSrcDataType(srcIdx)).reduce(_ ++ _) 257 } 258 259 def immType: Set[UInt] = fuConfigs.map(x => x.immType).reduce(_ ++ _) 260 261 def getWBSource: SchedulerType = { 262 schdType 263 } 264 265 def hasCrossWb: Boolean = { 266 schdType match { 267 case IntScheduler() => writeFpRf || writeVecRf 268 case VfScheduler() => writeIntRf 269 case _ => false 270 } 271 } 272 273 def canAccept(fuType: UInt): Bool = { 274 Cat(fuConfigs.map(_.fuType.U === fuType)).orR 275 } 276 277 def hasUncertainLatency: Boolean = fuConfigs.map(_.latency.latencyVal.isEmpty).reduce(_ || _) 278 279 def bindBackendParam(param: BackendParams): Unit = { 280 backendParam = param 281 } 282 283 def updateIQWakeUpConfigs(cfgs: Seq[WakeUpConfig]) = { 284 this.iqWakeUpSourcePairs = cfgs.filter(_.source.name == this.name) 285 this.iqWakeUpSinkPairs = cfgs.filter(_.sink.name == this.name) 286 if (this.isIQWakeUpSource) { 287 require(!this.hasUncertainLatency || hasLoadFu || hasHyldaFu, s"${this.name} is a not-LDU IQ wake up source , but has UncertainLatency") 288 } 289 } 290 291 def updateExuIdx(idx: Int): Unit = { 292 this.exuIdx = idx 293 } 294 295 def isIQWakeUpSource = this.iqWakeUpSourcePairs.nonEmpty 296 297 def isIQWakeUpSink = this.iqWakeUpSinkPairs.nonEmpty 298 299 def getIntWBPort = { 300 wbPortConfigs.collectFirst { 301 case x: IntWB => x 302 } 303 } 304 305 def getFpWBPort = { 306 wbPortConfigs.collectFirst { 307 case x: FpWB => x 308 } 309 } 310 311 def getVfWBPort = { 312 wbPortConfigs.collectFirst { 313 case x: VfWB => x 314 } 315 } 316 317 def getV0WBPort = { 318 wbPortConfigs.collectFirst { 319 case x: V0WB => x 320 } 321 } 322 323 def getVlWBPort = { 324 wbPortConfigs.collectFirst { 325 case x: VlWB => x 326 } 327 } 328 329 /** 330 * Get the [[DataConfig]] that this exu need to read 331 */ 332 def pregRdDataCfgSet: Set[DataConfig] = { 333 this.rfrPortConfigs.flatten.map(_.getDataConfig).toSet 334 } 335 336 /** 337 * Get the [[DataConfig]] that this exu need to write 338 */ 339 def pregWbDataCfgSet: Set[DataConfig] = { 340 this.wbPortConfigs.map(_.dataCfg).toSet 341 } 342 343 def getRfReadDataCfgSet: Seq[Set[DataConfig]] = { 344 val fuSrcsCfgSet: Seq[Seq[Set[DataConfig]]] = fuConfigs.map(_.getRfReadDataCfgSet) 345 val alignedFuSrcsCfgSet: Seq[Seq[Set[DataConfig]]] = fuSrcsCfgSet.map(x => x ++ Seq.fill(numRegSrc - x.length)(Set[DataConfig]())) 346 347 val exuSrcsCfgSet = alignedFuSrcsCfgSet.reduce((x, y) => (x zip y).map { case (cfg1, cfg2) => cfg1 union cfg2 }) 348 349 exuSrcsCfgSet 350 } 351 352 /** 353 * Get the [[DataConfig]] mapped indices of source data of exu 354 * 355 * @example 356 * {{{ 357 * fuCfg.srcData = Seq(VecData(), VecData(), VecData(), V0Data(), VlData()) 358 * getRfReadSrcIdx(VecData()) = Seq(0, 1, 2) 359 * getRfReadSrcIdx(V0Data()) = Seq(3) 360 * getRfReadSrcIdx(VlData()) = Seq(4) 361 * }}} 362 * @return Map[DataConfig -> Seq[indices]] 363 */ 364 def getRfReadSrcIdx: Map[DataConfig, Seq[Int]] = { 365 val dataCfgs = DataConfig.RegSrcDataSet 366 val rfRdDataCfgSet = this.getRfReadDataCfgSet 367 dataCfgs.toSeq.map { cfg => 368 ( 369 cfg, 370 rfRdDataCfgSet.zipWithIndex.map { case (set, srcIdx) => 371 if (set.contains(cfg)) 372 Option(srcIdx) 373 else 374 None 375 }.filter(_.nonEmpty).map(_.get) 376 ) 377 }.toMap 378 } 379 380 def genExuModule(implicit p: Parameters): ExeUnit = { 381 new ExeUnit(this) 382 } 383 384 def genExuInputBundle(implicit p: Parameters): ExuInput = { 385 new ExuInput(this) 386 } 387 388 def genExuOutputBundle(implicit p: Parameters): ExuOutput = { 389 new ExuOutput(this) 390 } 391 392 def genExuBypassBundle(implicit p: Parameters): ExuBypassBundle = { 393 new ExuBypassBundle(this) 394 } 395} 396