1package xiangshan.backend.exu 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import xiangshan.backend.BackendParams 7import xiangshan.backend.Bundles.{ExuBypassBundle, ExuInput, ExuOutput} 8import xiangshan.backend.datapath.DataConfig.DataConfig 9import xiangshan.backend.datapath.RdConfig._ 10import xiangshan.backend.datapath.WbConfig._ 11import xiangshan.backend.datapath.{DataConfig, WakeUpConfig} 12import xiangshan.backend.fu.{FuConfig, FuType} 13import xiangshan.backend.issue.{IssueBlockParams, SchedulerType, IntScheduler, VfScheduler, MemScheduler} 14import scala.collection.mutable 15 16case class ExeUnitParams( 17 name : String, 18 fuConfigs : Seq[FuConfig], 19 wbPortConfigs : Seq[PregWB], 20 rfrPortConfigs: Seq[Seq[RdConfig]], 21 copyWakeupOut: Boolean = false, 22 copyDistance: Int = 1, 23 fakeUnit : Boolean = false, 24)( 25 implicit 26 val schdType: SchedulerType, 27) { 28 // calculated configs 29 var iqWakeUpSourcePairs: Seq[WakeUpConfig] = Seq() 30 var iqWakeUpSinkPairs: Seq[WakeUpConfig] = Seq() 31 var needLoadDependency: Boolean = false 32 // used in bypass to select data of exu output 33 var exuIdx: Int = -1 34 var backendParam: BackendParams = null 35 36 val numIntSrc: Int = fuConfigs.map(_.numIntSrc).max 37 val numFpSrc: Int = fuConfigs.map(_.numFpSrc).max 38 val numVecSrc: Int = fuConfigs.map(_.numVecSrc).max 39 val numVfSrc: Int = fuConfigs.map(_.numVfSrc).max 40 val numV0Src: Int = fuConfigs.map(_.numV0Src).max 41 val numVlSrc: Int = fuConfigs.map(_.numVlSrc).max 42 val numRegSrc: Int = fuConfigs.map(_.numRegSrc).max 43 val numSrc: Int = fuConfigs.map(_.numSrc).max 44 val destDataBitsMax: Int = fuConfigs.map(_.destDataBits).max 45 val srcDataBitsMax: Int = fuConfigs.map(x => x.srcDataBits.getOrElse(x.destDataBits)).max 46 val readIntRf: Boolean = numIntSrc > 0 47 val readFpRf: Boolean = numFpSrc > 0 48 val readVecRf: Boolean = numVecSrc > 0 49 val readVfRf: Boolean = numVfSrc > 0 50 val readVlRf: Boolean = numVlSrc > 0 51 val writeIntRf: Boolean = fuConfigs.map(_.writeIntRf).reduce(_ || _) 52 val writeFpRf: Boolean = fuConfigs.map(_.writeFpRf).reduce(_ || _) 53 val writeVecRf: Boolean = fuConfigs.map(_.writeVecRf).reduce(_ || _) 54 val writeV0Rf: Boolean = fuConfigs.map(_.writeV0Rf).reduce(_ || _) 55 val writeVlRf: Boolean = fuConfigs.map(_.writeVlRf).reduce(_ || _) 56 val needIntWen: Boolean = fuConfigs.map(_.needIntWen).reduce(_ || _) 57 val needFpWen: Boolean = fuConfigs.map(_.needFpWen).reduce(_ || _) 58 val needVecWen: Boolean = fuConfigs.map(_.needVecWen).reduce(_ || _) 59 val needV0Wen: Boolean = fuConfigs.map(_.needV0Wen).reduce(_ || _) 60 val needVlWen: Boolean = fuConfigs.map(_.needVlWen).reduce(_ || _) 61 val needOg2: Boolean = fuConfigs.map(_.needOg2).reduce(_ || _) 62 val writeVfRf: Boolean = writeVecRf 63 val writeFflags: Boolean = fuConfigs.map(_.writeFflags).reduce(_ || _) 64 val writeVxsat: Boolean = fuConfigs.map(_.writeVxsat).reduce(_ || _) 65 val hasNoDataWB: Boolean = fuConfigs.map(_.hasNoDataWB).reduce(_ && _) 66 val hasRedirect: Boolean = fuConfigs.map(_.hasRedirect).reduce(_ || _) 67 val hasPredecode: Boolean = fuConfigs.map(_.hasPredecode).reduce(_ || _) 68 val exceptionOut: Seq[Int] = fuConfigs.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted 69 val hasLoadError: Boolean = fuConfigs.map(_.hasLoadError).reduce(_ || _) 70 val flushPipe: Boolean = fuConfigs.map(_.flushPipe).reduce(_ || _) 71 val replayInst: Boolean = fuConfigs.map(_.replayInst).reduce(_ || _) 72 val trigger: Boolean = fuConfigs.map(_.trigger).reduce(_ || _) 73 val needExceptionGen: Boolean = exceptionOut.nonEmpty || flushPipe || replayInst || trigger 74 val needPc: Boolean = fuConfigs.map(_.needPc).reduce(_ || _) 75 val needTarget: Boolean = fuConfigs.map(_.needTargetPc).reduce(_ || _) 76 val needPdInfo: Boolean = fuConfigs.map(_.needPdInfo).reduce(_ || _) 77 val needSrcFrm: Boolean = fuConfigs.map(_.needSrcFrm).reduce(_ || _) 78 val needSrcVxrm: Boolean = fuConfigs.map(_.needSrcVxrm).reduce(_ || _) 79 val needFPUCtrl: Boolean = fuConfigs.map(_.needFPUCtrl).reduce(_ || _) 80 val needVPUCtrl: Boolean = fuConfigs.map(_.needVecCtrl).reduce(_ || _) 81 val writeVConfig: Boolean = fuConfigs.map(_.writeVlRf).reduce(_ || _) 82 val writeVType: Boolean = fuConfigs.map(_.writeVType).reduce(_ || _) 83 val needCriticalErrors: Boolean = fuConfigs.map(_.needCriticalErrors).reduce(_ || _) 84 val isHighestWBPriority: Boolean = wbPortConfigs.forall(_.priority == 0) 85 86 val isIntExeUnit: Boolean = schdType.isInstanceOf[IntScheduler] 87 val isVfExeUnit: Boolean = schdType.isInstanceOf[VfScheduler] 88 val isMemExeUnit: Boolean = schdType.isInstanceOf[MemScheduler] 89 90 def needReadRegCache: Boolean = isIntExeUnit || isMemExeUnit && readIntRf 91 def needWriteRegCache: Boolean = isIntExeUnit && isIQWakeUpSource || isMemExeUnit && isIQWakeUpSource && readIntRf 92 93 // exu writeback: 0 normalout; 1 intout; 2 fpout; 3 vecout 94 val wbNeedIntWen : Boolean = writeIntRf && !isMemExeUnit 95 val wbNeedFpWen : Boolean = writeFpRf && !isMemExeUnit 96 val wbNeedVecWen : Boolean = writeVecRf && !isMemExeUnit 97 val wbNeedV0Wen : Boolean = writeV0Rf && !isMemExeUnit 98 val wbNeedVlWen : Boolean = writeVlRf && !isMemExeUnit 99 val wbPathNum: Int = Seq(wbNeedIntWen, wbNeedFpWen, wbNeedVecWen, wbNeedV0Wen, wbNeedVlWen).count(_ == true) + 1 100 val wbNeeds = Seq( 101 ("int", wbNeedIntWen), 102 ("fp", wbNeedFpWen), 103 ("vec", wbNeedVecWen), 104 ("v0", wbNeedV0Wen), 105 ("vl", wbNeedVlWen) 106 ) 107 val wbIndexeds = wbNeeds.filter(_._2).zipWithIndex.map { 108 case ((label, _), index) => (label, index + 1) 109 }.toMap 110 val wbIntIndex: Int = wbIndexeds.getOrElse("int", 0) 111 val wbFpIndex : Int = wbIndexeds.getOrElse("fp", 0) 112 val wbVecIndex: Int = wbIndexeds.getOrElse("vec", 0) 113 val wbV0Index : Int = wbIndexeds.getOrElse("v0" , 0) 114 val wbVlIndex : Int = wbIndexeds.getOrElse("vl" , 0) 115 val wbIndex: Seq[Int] = Seq(wbIntIndex, wbFpIndex, wbVecIndex, wbV0Index, wbVlIndex) 116 117 118 119 require(needPc && needTarget || !needPc && !needTarget, "The ExeUnit must need both PC and Target PC") 120 121 def copyNum: Int = { 122 val setIQ = mutable.Set[IssueBlockParams]() 123 iqWakeUpSourcePairs.map(_.sink).foreach{ wakeupSink => 124 backendParam.allIssueParams.map{ issueParams => 125 if (issueParams.exuBlockParams.contains(wakeupSink.getExuParam(backendParam.allExuParams))) { 126 setIQ.add(issueParams) 127 } 128 } 129 } 130 println(s"[Backend] exuIdx ${exuIdx} numWakeupIQ ${setIQ.size}") 131 1 + setIQ.size / copyDistance 132 } 133 def rdPregIdxWidth: Int = { 134 this.pregRdDataCfgSet.map(dataCfg => backendParam.getPregParams(dataCfg).addrWidth).fold(0)(_ max _) 135 } 136 137 def wbPregIdxWidth: Int = { 138 this.pregWbDataCfgSet.map(dataCfg => backendParam.getPregParams(dataCfg).addrWidth).fold(0)(_ max _) 139 } 140 141 val writeIntFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeIntRf) 142 val writeFpFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeFpRf) 143 val writeVfFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeVecRf) 144 val writeV0FuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeV0Rf) 145 val writeVlFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeVlRf) 146 147 /** 148 * Check if this exu has certain latency 149 */ 150 def latencyCertain: Boolean = fuConfigs.map(x => x.latency.latencyVal.nonEmpty).reduce(_ && _) 151 def intLatencyCertain: Boolean = writeIntFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 152 def fpLatencyCertain: Boolean = writeFpFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 153 def vfLatencyCertain: Boolean = writeVfFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 154 def v0LatencyCertain: Boolean = writeV0FuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 155 def vlLatencyCertain: Boolean = writeVlFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 156 // only load use it 157 def hasUncertainLatencyVal: Boolean = fuConfigs.map(x => x.latency.uncertainLatencyVal.nonEmpty).reduce(_ || _) 158 159 /** 160 * Get mapping from FuType to Latency value. 161 * If both [[latencyCertain]] and [[hasUncertainLatencyVal]] are false, get empty [[Map]] 162 * 163 * @return Map[ [[BigInt]], Latency] 164 */ 165 def fuLatencyMap: Map[FuType.OHType, Int] = { 166 if (latencyCertain) 167 if(needOg2) fuConfigs.map(x => (x.fuType, x.latency.latencyVal.get + 1)).toMap else fuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 168 else if (hasUncertainLatencyVal) 169 fuConfigs.map(x => (x.fuType, x.latency.uncertainLatencyVal)).toMap.filter(_._2.nonEmpty).map(x => (x._1, x._2.get)) 170 else 171 Map() 172 } 173 def wakeUpFuLatencyMap: Map[FuType.OHType, Int] = { 174 if (latencyCertain) 175 fuConfigs.filterNot(_.hasNoDataWB).map(x => (x.fuType, x.latency.latencyVal.get)).toMap 176 else if (hasUncertainLatencyVal) 177 fuConfigs.filterNot(_.hasNoDataWB).map(x => (x.fuType, x.latency.uncertainLatencyVal.get)).toMap 178 else 179 Map() 180 } 181 182 /** 183 * Get set of latency of function units. 184 * If both [[latencyCertain]] and [[hasUncertainLatencyVal]] are false, get empty [[Set]] 185 * 186 * @return Set[Latency] 187 */ 188 def fuLatancySet: Set[Int] = fuLatencyMap.values.toSet 189 190 def wakeUpFuLatancySet: Set[Int] = wakeUpFuLatencyMap.values.toSet 191 192 def latencyValMax: Int = fuLatancySet.fold(0)(_ max _) 193 194 def intFuLatencyMap: Map[FuType.OHType, Int] = { 195 if (intLatencyCertain) { 196 if (isVfExeUnit) { 197 // vf exe unit writing back to int regfile should delay 1 cycle 198 // vf exe unit need og2 --> delay 1 cycle 199 writeIntFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get + 2)).toMap 200 } else { 201 writeIntFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 202 } 203 } 204 else 205 Map() 206 } 207 208 def intLatencyValMax: Int = intFuLatencyMap.values.fold(0)(_ max _) 209 210 def fpFuLatencyMap: Map[FuType.OHType, Int] = { 211 if (fpLatencyCertain) 212 if (needOg2) writeFpFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get + 1)).toMap else writeFpFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 213 else 214 Map() 215 } 216 217 def fpLatencyValMax: Int = fpFuLatencyMap.values.fold(0)(_ max _) 218 219 def vfFuLatencyMap: Map[FuType.OHType, Int] = { 220 if (vfLatencyCertain) 221 if(needOg2) writeVfFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get + 1)).toMap else writeVfFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 222 else 223 Map() 224 } 225 226 def vfLatencyValMax: Int = vfFuLatencyMap.values.fold(0)(_ max _) 227 228 def v0FuLatencyMap: Map[FuType.OHType, Int] = { 229 if (v0LatencyCertain) 230 if(needOg2) writeV0FuConfigs.map(x => (x.fuType, x.latency.latencyVal.get + 1)).toMap else writeV0FuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 231 else 232 Map() 233 } 234 235 def v0LatencyValMax: Int = v0FuLatencyMap.values.fold(0)(_ max _) 236 237 def vlFuLatencyMap: Map[FuType.OHType, Int] = { 238 if (vlLatencyCertain) 239 if(needOg2) writeVlFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get + 1)).toMap else writeVlFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 240 else 241 Map() 242 } 243 244 def vlLatencyValMax: Int = vlFuLatencyMap.values.fold(0)(_ max _) 245 246 /** 247 * Check if this exu has fixed latency 248 */ 249 def isFixedLatency: Boolean = { 250 if (latencyCertain) 251 return fuConfigs.map(x => x.latency.latencyVal.get == fuConfigs.head.latency.latencyVal.get).reduce(_ && _) 252 false 253 } 254 255 def hasCSR: Boolean = fuConfigs.map(_.isCsr).reduce(_ || _) 256 257 def hasFence: Boolean = fuConfigs.map(_.isFence).reduce(_ || _) 258 259 def hasBrhFu = fuConfigs.map(_.fuType == FuType.brh).reduce(_ || _) 260 261 def hasi2vFu = fuConfigs.map(_.fuType == FuType.i2v).reduce(_ || _) 262 263 def hasJmpFu = fuConfigs.map(_.fuType == FuType.jmp).reduce(_ || _) 264 265 def hasLoadFu = fuConfigs.map(_.name == "ldu").reduce(_ || _) 266 267 def hasVLoadFu = fuConfigs.map(_.fuType == FuType.vldu).reduce(_ || _) 268 269 def hasVStoreFu = fuConfigs.map(_.fuType == FuType.vstu).reduce(_ || _) 270 271 def hasVecLsFu = fuConfigs.map(x => FuType.FuTypeOrR(x.fuType, Seq(FuType.vldu, FuType.vstu))).reduce(_ || _) 272 273 def hasStoreAddrFu = fuConfigs.map(_.name == "sta").reduce(_ || _) 274 275 def hasStdFu = fuConfigs.map(_.name == "std").reduce(_ || _) 276 277 def hasMemAddrFu = hasLoadFu || hasStoreAddrFu || hasVLoadFu || hasHyldaFu || hasHystaFu || hasVLoadFu || hasVStoreFu 278 279 def hasHyldaFu = fuConfigs.map(_.name == "hylda").reduce(_ || _) 280 281 def hasHystaFu = fuConfigs.map(_.name == "hysta").reduce(_ || _) 282 283 def hasLoadExu = hasLoadFu || hasHyldaFu 284 285 def hasStoreAddrExu = hasStoreAddrFu || hasHystaFu 286 287 def hasVecFu = fuConfigs.map(x => FuConfig.VecArithFuConfigs.contains(x)).reduce(_ || _) 288 289 def CanCompress = !hasBrhFu || (hasBrhFu && hasi2vFu) 290 291 def getSrcDataType(srcIdx: Int): Set[DataConfig] = { 292 fuConfigs.map(_.getSrcDataType(srcIdx)).reduce(_ ++ _) 293 } 294 295 def immType: Set[UInt] = fuConfigs.map(x => x.immType).reduce(_ ++ _) 296 297 def getWBSource: SchedulerType = { 298 schdType 299 } 300 301 def hasCrossWb: Boolean = { 302 schdType match { 303 case IntScheduler() => writeFpRf || writeVecRf 304 case VfScheduler() => writeIntRf 305 case _ => false 306 } 307 } 308 309 def canAccept(fuType: UInt): Bool = { 310 Cat(fuConfigs.map(_.fuType.U === fuType)).orR 311 } 312 313 def hasUncertainLatency: Boolean = fuConfigs.map(_.latency.latencyVal.isEmpty).reduce(_ || _) 314 315 def bindBackendParam(param: BackendParams): Unit = { 316 backendParam = param 317 } 318 319 def updateIQWakeUpConfigs(cfgs: Seq[WakeUpConfig]) = { 320 this.iqWakeUpSourcePairs = cfgs.filter(_.source.name == this.name) 321 this.iqWakeUpSinkPairs = cfgs.filter(_.sink.name == this.name) 322 if (this.isIQWakeUpSource) { 323 require(!this.hasUncertainLatency || hasLoadFu || hasHyldaFu, s"${this.name} is a not-LDU IQ wake up source , but has UncertainLatency") 324 } 325 val loadWakeUpSourcePairs = cfgs.filter(x => x.source.getExuParam(backendParam.allExuParams).hasLoadFu || x.source.getExuParam(backendParam.allExuParams).hasHyldaFu) 326 val wakeUpByLoadNames = loadWakeUpSourcePairs.map(_.sink.name).toSet 327 val thisWakeUpByNames = iqWakeUpSinkPairs.map(_.source.name).toSet 328 this.needLoadDependency = !(wakeUpByLoadNames & thisWakeUpByNames).isEmpty 329 println(s"${this.name}: needLoadDependency is ${this.needLoadDependency}") 330 } 331 332 def updateExuIdx(idx: Int): Unit = { 333 this.exuIdx = idx 334 } 335 336 def isIQWakeUpSource = this.iqWakeUpSourcePairs.nonEmpty 337 338 def isIQWakeUpSink = this.iqWakeUpSinkPairs.nonEmpty 339 340 def numWakeupFromIQ = this.iqWakeUpSinkPairs.size 341 342 def getIntWBPort = { 343 wbPortConfigs.collectFirst { 344 case x: IntWB => x 345 } 346 } 347 348 def getFpWBPort = { 349 wbPortConfigs.collectFirst { 350 case x: FpWB => x 351 } 352 } 353 354 def getVfWBPort = { 355 wbPortConfigs.collectFirst { 356 case x: VfWB => x 357 } 358 } 359 360 def getV0WBPort = { 361 wbPortConfigs.collectFirst { 362 case x: V0WB => x 363 } 364 } 365 366 def getVlWBPort = { 367 wbPortConfigs.collectFirst { 368 case x: VlWB => x 369 } 370 } 371 372 /** 373 * Get the [[DataConfig]] that this exu need to read 374 */ 375 def pregRdDataCfgSet: Set[DataConfig] = { 376 this.rfrPortConfigs.flatten.map(_.getDataConfig).toSet 377 } 378 379 /** 380 * Get the [[DataConfig]] that this exu need to write 381 */ 382 def pregWbDataCfgSet: Set[DataConfig] = { 383 this.wbPortConfigs.map(_.dataCfg).toSet 384 } 385 386 def getRfReadDataCfgSet: Seq[Set[DataConfig]] = { 387 val fuSrcsCfgSet: Seq[Seq[Set[DataConfig]]] = fuConfigs.map(_.getRfReadDataCfgSet) 388 val alignedFuSrcsCfgSet: Seq[Seq[Set[DataConfig]]] = fuSrcsCfgSet.map(x => x ++ Seq.fill(numRegSrc - x.length)(Set[DataConfig]())) 389 390 val exuSrcsCfgSet = alignedFuSrcsCfgSet.reduce((x, y) => (x zip y).map { case (cfg1, cfg2) => cfg1 union cfg2 }) 391 392 exuSrcsCfgSet 393 } 394 395 /** 396 * Get the [[DataConfig]] mapped indices of source data of exu 397 * 398 * @example 399 * {{{ 400 * fuCfg.srcData = Seq(VecData(), VecData(), VecData(), V0Data(), VlData()) 401 * getRfReadSrcIdx(VecData()) = Seq(0, 1, 2) 402 * getRfReadSrcIdx(V0Data()) = Seq(3) 403 * getRfReadSrcIdx(VlData()) = Seq(4) 404 * }}} 405 * @return Map[DataConfig -> Seq[indices]] 406 */ 407 def getRfReadSrcIdx: Map[DataConfig, Seq[Int]] = { 408 val dataCfgs = DataConfig.RegSrcDataSet 409 val rfRdDataCfgSet = this.getRfReadDataCfgSet 410 dataCfgs.toSeq.map { cfg => 411 ( 412 cfg, 413 rfRdDataCfgSet.zipWithIndex.map { case (set, srcIdx) => 414 if (set.contains(cfg)) 415 Option(srcIdx) 416 else 417 None 418 }.filter(_.nonEmpty).map(_.get) 419 ) 420 }.toMap 421 } 422 423 def genExuModule(implicit p: Parameters): ExeUnit = { 424 new ExeUnit(this) 425 } 426 427 def genExuInputBundle(implicit p: Parameters): ExuInput = { 428 new ExuInput(this) 429 } 430 431 def genExuOutputBundle(implicit p: Parameters): ExuOutput = { 432 new ExuOutput(this) 433 } 434 435 def genExuBypassBundle(implicit p: Parameters): ExuBypassBundle = { 436 new ExuBypassBundle(this) 437 } 438} 439