1package xiangshan.backend.exu 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import xiangshan.backend.BackendParams 7import xiangshan.backend.Bundles.{ExuBypassBundle, ExuInput, ExuOutput} 8import xiangshan.backend.datapath.DataConfig.DataConfig 9import xiangshan.backend.datapath.RdConfig._ 10import xiangshan.backend.datapath.WbConfig._ 11import xiangshan.backend.datapath.{DataConfig, WakeUpConfig} 12import xiangshan.backend.fu.{FuConfig, FuType} 13import xiangshan.backend.issue.{IssueBlockParams, SchedulerType, IntScheduler, VfScheduler, MemScheduler} 14import scala.collection.mutable 15 16case class ExeUnitParams( 17 name : String, 18 fuConfigs : Seq[FuConfig], 19 wbPortConfigs : Seq[PregWB], 20 rfrPortConfigs: Seq[Seq[RdConfig]], 21 copyWakeupOut: Boolean = false, 22 copyDistance: Int = 1, 23 fakeUnit : Boolean = false, 24)( 25 implicit 26 val schdType: SchedulerType, 27) { 28 // calculated configs 29 var iqWakeUpSourcePairs: Seq[WakeUpConfig] = Seq() 30 var iqWakeUpSinkPairs: Seq[WakeUpConfig] = Seq() 31 // used in bypass to select data of exu output 32 var exuIdx: Int = -1 33 var backendParam: BackendParams = null 34 35 val numIntSrc: Int = fuConfigs.map(_.numIntSrc).max 36 val numFpSrc: Int = fuConfigs.map(_.numFpSrc).max 37 val numVecSrc: Int = fuConfigs.map(_.numVecSrc).max 38 val numVfSrc: Int = fuConfigs.map(_.numVfSrc).max 39 val numV0Src: Int = fuConfigs.map(_.numV0Src).max 40 val numVlSrc: Int = fuConfigs.map(_.numVlSrc).max 41 val numRegSrc: Int = fuConfigs.map(_.numRegSrc).max 42 val numSrc: Int = fuConfigs.map(_.numSrc).max 43 val dataBitsMax: Int = fuConfigs.map(_.dataBits).max 44 val readIntRf: Boolean = numIntSrc > 0 45 val readFpRf: Boolean = numFpSrc > 0 46 val readVecRf: Boolean = numVecSrc > 0 47 val readVfRf: Boolean = numVfSrc > 0 48 val writeIntRf: Boolean = fuConfigs.map(_.writeIntRf).reduce(_ || _) 49 val writeFpRf: Boolean = fuConfigs.map(_.writeFpRf).reduce(_ || _) 50 val writeVecRf: Boolean = fuConfigs.map(_.writeVecRf).reduce(_ || _) 51 val needIntWen: Boolean = fuConfigs.map(_.needIntWen).reduce(_ || _) 52 val needFpWen: Boolean = fuConfigs.map(_.needFpWen).reduce(_ || _) 53 val needVecWen: Boolean = fuConfigs.map(_.needVecWen).reduce(_ || _) 54 val needV0Wen: Boolean = fuConfigs.map(_.needV0Wen).reduce(_ || _) 55 val needVlWen: Boolean = fuConfigs.map(_.needVlWen).reduce(_ || _) 56 val needOg2: Boolean = fuConfigs.map(_.needOg2).reduce(_ || _) 57 val writeVfRf: Boolean = writeVecRf 58 val writeFflags: Boolean = fuConfigs.map(_.writeFflags).reduce(_ || _) 59 val writeVxsat: Boolean = fuConfigs.map(_.writeVxsat).reduce(_ || _) 60 val hasNoDataWB: Boolean = fuConfigs.map(_.hasNoDataWB).reduce(_ && _) 61 val hasRedirect: Boolean = fuConfigs.map(_.hasRedirect).reduce(_ || _) 62 val hasPredecode: Boolean = fuConfigs.map(_.hasPredecode).reduce(_ || _) 63 val exceptionOut: Seq[Int] = fuConfigs.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted 64 val hasLoadError: Boolean = fuConfigs.map(_.hasLoadError).reduce(_ || _) 65 val flushPipe: Boolean = fuConfigs.map(_.flushPipe).reduce(_ || _) 66 val replayInst: Boolean = fuConfigs.map(_.replayInst).reduce(_ || _) 67 val trigger: Boolean = fuConfigs.map(_.trigger).reduce(_ || _) 68 val needExceptionGen: Boolean = exceptionOut.nonEmpty || flushPipe || replayInst || trigger 69 val needPc: Boolean = fuConfigs.map(_.needPc).reduce(_ || _) 70 val needTarget: Boolean = fuConfigs.map(_.needTargetPc).reduce(_ || _) 71 val needPdInfo: Boolean = fuConfigs.map(_.needPdInfo).reduce(_ || _) 72 val needSrcFrm: Boolean = fuConfigs.map(_.needSrcFrm).reduce(_ || _) 73 val needSrcVxrm: Boolean = fuConfigs.map(_.needSrcVxrm).reduce(_ || _) 74 val needFPUCtrl: Boolean = fuConfigs.map(_.needFPUCtrl).reduce(_ || _) 75 val needVPUCtrl: Boolean = fuConfigs.map(_.needVecCtrl).reduce(_ || _) 76 val writeVConfig: Boolean = fuConfigs.map(_.writeVConfig).reduce(_ || _) 77 val writeVType: Boolean = fuConfigs.map(_.writeVType).reduce(_ || _) 78 val isHighestWBPriority: Boolean = wbPortConfigs.forall(_.priority == 0) 79 80 val isIntExeUnit: Boolean = schdType.isInstanceOf[IntScheduler] 81 val isVfExeUnit: Boolean = schdType.isInstanceOf[VfScheduler] 82 val isMemExeUnit: Boolean = schdType.isInstanceOf[MemScheduler] 83 84 require(needPc && needTarget || !needPc && !needTarget, "The ExeUnit must need both PC and Target PC") 85 86 def copyNum: Int = { 87 val setIQ = mutable.Set[IssueBlockParams]() 88 iqWakeUpSourcePairs.map(_.sink).foreach{ wakeupSink => 89 backendParam.allIssueParams.map{ issueParams => 90 if (issueParams.exuBlockParams.contains(wakeupSink.getExuParam(backendParam.allExuParams))) { 91 setIQ.add(issueParams) 92 } 93 } 94 } 95 println(s"[Backend] exuIdx ${exuIdx} numWakeupIQ ${setIQ.size}") 96 1 + setIQ.size / copyDistance 97 } 98 def rdPregIdxWidth: Int = { 99 this.pregRdDataCfgSet.map(dataCfg => backendParam.getPregParams(dataCfg).addrWidth).fold(0)(_ max _) 100 } 101 102 def wbPregIdxWidth: Int = { 103 this.pregWbDataCfgSet.map(dataCfg => backendParam.getPregParams(dataCfg).addrWidth).fold(0)(_ max _) 104 } 105 106 val writeIntFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeIntRf) 107 val writeFpFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeFpRf) 108 val writeVfFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeVecRf) 109 val writeV0FuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeV0Rf) 110 val writeVlFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeVlRf) 111 112 /** 113 * Check if this exu has certain latency 114 */ 115 def latencyCertain: Boolean = fuConfigs.map(x => x.latency.latencyVal.nonEmpty).reduce(_ && _) 116 def intLatencyCertain: Boolean = writeIntFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 117 def fpLatencyCertain: Boolean = writeFpFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 118 def vfLatencyCertain: Boolean = writeVfFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 119 def v0LatencyCertain: Boolean = writeV0FuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 120 def vlLatencyCertain: Boolean = writeVlFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 121 // only load use it 122 def hasUncertainLatencyVal: Boolean = fuConfigs.map(x => x.latency.uncertainLatencyVal.nonEmpty).reduce(_ || _) 123 124 /** 125 * Get mapping from FuType to Latency value. 126 * If both [[latencyCertain]] and [[hasUncertainLatencyVal]] are false, get empty [[Map]] 127 * 128 * @return Map[ [[BigInt]], Latency] 129 */ 130 def fuLatencyMap: Map[FuType.OHType, Int] = { 131 if (latencyCertain) 132 if(needOg2) fuConfigs.map(x => (x.fuType, x.latency.latencyVal.get + 1)).toMap else fuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 133 else if (hasUncertainLatencyVal) 134 fuConfigs.map(x => (x.fuType, x.latency.uncertainLatencyVal)).toMap.filter(_._2.nonEmpty).map(x => (x._1, x._2.get)) 135 else 136 Map() 137 } 138 def wakeUpFuLatencyMap: Map[FuType.OHType, Int] = { 139 if (latencyCertain) 140 fuConfigs.filterNot(_.hasNoDataWB).map(x => (x.fuType, x.latency.latencyVal.get)).toMap 141 else if (hasUncertainLatencyVal) 142 fuConfigs.filterNot(_.hasNoDataWB).map(x => (x.fuType, x.latency.uncertainLatencyVal.get)).toMap 143 else 144 Map() 145 } 146 147 /** 148 * Get set of latency of function units. 149 * If both [[latencyCertain]] and [[hasUncertainLatencyVal]] are false, get empty [[Set]] 150 * 151 * @return Set[Latency] 152 */ 153 def fuLatancySet: Set[Int] = fuLatencyMap.values.toSet 154 155 def wakeUpFuLatancySet: Set[Int] = wakeUpFuLatencyMap.values.toSet 156 157 def latencyValMax: Int = fuLatancySet.fold(0)(_ max _) 158 159 def intFuLatencyMap: Map[FuType.OHType, Int] = { 160 if (intLatencyCertain) { 161 if (isVfExeUnit) { 162 // vf exe unit writing back to int regfile should delay 1 cycle 163 // vf exe unit need og2 --> delay 1 cycle 164 writeIntFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get + 2)).toMap 165 } else { 166 writeIntFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 167 } 168 } 169 else 170 Map() 171 } 172 173 def intLatencyValMax: Int = intFuLatencyMap.values.fold(0)(_ max _) 174 175 def fpFuLatencyMap: Map[FuType.OHType, Int] = { 176 if (fpLatencyCertain) 177 writeFpFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 178 else 179 Map() 180 } 181 182 def fpLatencyValMax: Int = fpFuLatencyMap.values.fold(0)(_ max _) 183 184 def vfFuLatencyMap: Map[FuType.OHType, Int] = { 185 if (vfLatencyCertain) 186 if(needOg2) writeVfFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get + 1)).toMap else writeVfFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 187 else 188 Map() 189 } 190 191 def vfLatencyValMax: Int = vfFuLatencyMap.values.fold(0)(_ max _) 192 193 def v0FuLatencyMap: Map[FuType.OHType, Int] = { 194 if (v0LatencyCertain) 195 if(needOg2) writeV0FuConfigs.map(x => (x.fuType, x.latency.latencyVal.get + 1)).toMap else writeV0FuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 196 else 197 Map() 198 } 199 200 def v0LatencyValMax: Int = v0FuLatencyMap.values.fold(0)(_ max _) 201 202 def vlFuLatencyMap: Map[FuType.OHType, Int] = { 203 if (vlLatencyCertain) 204 if(needOg2) writeVlFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get + 1)).toMap else writeVlFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 205 else 206 Map() 207 } 208 209 def vlLatencyValMax: Int = vlFuLatencyMap.values.fold(0)(_ max _) 210 211 /** 212 * Check if this exu has fixed latency 213 */ 214 def isFixedLatency: Boolean = { 215 if (latencyCertain) 216 return fuConfigs.map(x => x.latency.latencyVal.get == fuConfigs.head.latency.latencyVal.get).reduce(_ && _) 217 false 218 } 219 220 def hasCSR: Boolean = fuConfigs.map(_.isCsr).reduce(_ || _) 221 222 def hasFence: Boolean = fuConfigs.map(_.isFence).reduce(_ || _) 223 224 def hasBrhFu = fuConfigs.map(_.fuType == FuType.brh).reduce(_ || _) 225 226 def hasJmpFu = fuConfigs.map(_.fuType == FuType.jmp).reduce(_ || _) 227 228 def hasLoadFu = fuConfigs.map(_.name == "ldu").reduce(_ || _) 229 230 def hasVLoadFu = fuConfigs.map(_.fuType == FuType.vldu).reduce(_ || _) 231 232 def hasVStoreFu = fuConfigs.map(_.fuType == FuType.vstu).reduce(_ || _) 233 234 def hasVecLsFu = fuConfigs.map(x => FuType.FuTypeOrR(x.fuType, Seq(FuType.vldu, FuType.vstu))).reduce(_ || _) 235 236 def hasStoreAddrFu = fuConfigs.map(_.name == "sta").reduce(_ || _) 237 238 def hasStdFu = fuConfigs.map(_.name == "std").reduce(_ || _) 239 240 def hasMemAddrFu = hasLoadFu || hasStoreAddrFu || hasVLoadFu || hasHyldaFu || hasHystaFu || hasVLoadFu || hasVStoreFu 241 242 def hasHyldaFu = fuConfigs.map(_.name == "hylda").reduce(_ || _) 243 244 def hasHystaFu = fuConfigs.map(_.name == "hysta").reduce(_ || _) 245 246 def hasLoadExu = hasLoadFu || hasHyldaFu 247 248 def hasStoreAddrExu = hasStoreAddrFu || hasHystaFu 249 250 def hasVecFu = fuConfigs.map(x => FuConfig.VecArithFuConfigs.contains(x)).reduce(_ || _) 251 252 def getSrcDataType(srcIdx: Int): Set[DataConfig] = { 253 fuConfigs.map(_.getSrcDataType(srcIdx)).reduce(_ ++ _) 254 } 255 256 def immType: Set[UInt] = fuConfigs.map(x => x.immType).reduce(_ ++ _) 257 258 def getWBSource: SchedulerType = { 259 schdType 260 } 261 262 def hasCrossWb: Boolean = { 263 schdType match { 264 case IntScheduler() => writeFpRf || writeVecRf 265 case VfScheduler() => writeIntRf 266 case _ => false 267 } 268 } 269 270 def canAccept(fuType: UInt): Bool = { 271 Cat(fuConfigs.map(_.fuType.U === fuType)).orR 272 } 273 274 def hasUncertainLatency: Boolean = fuConfigs.map(_.latency.latencyVal.isEmpty).reduce(_ || _) 275 276 def bindBackendParam(param: BackendParams): Unit = { 277 backendParam = param 278 } 279 280 def updateIQWakeUpConfigs(cfgs: Seq[WakeUpConfig]) = { 281 this.iqWakeUpSourcePairs = cfgs.filter(_.source.name == this.name) 282 this.iqWakeUpSinkPairs = cfgs.filter(_.sink.name == this.name) 283 if (this.isIQWakeUpSource) { 284 require(!this.hasUncertainLatency || hasLoadFu || hasHyldaFu, s"${this.name} is a not-LDU IQ wake up source , but has UncertainLatency") 285 } 286 } 287 288 def updateExuIdx(idx: Int): Unit = { 289 this.exuIdx = idx 290 } 291 292 def isIQWakeUpSource = this.iqWakeUpSourcePairs.nonEmpty 293 294 def isIQWakeUpSink = this.iqWakeUpSinkPairs.nonEmpty 295 296 def getIntWBPort = { 297 wbPortConfigs.collectFirst { 298 case x: IntWB => x 299 } 300 } 301 302 def getFpWBPort = { 303 wbPortConfigs.collectFirst { 304 case x: FpWB => x 305 } 306 } 307 308 def getVfWBPort = { 309 wbPortConfigs.collectFirst { 310 case x: VfWB => x 311 } 312 } 313 314 def getV0WBPort = { 315 wbPortConfigs.collectFirst { 316 case x: V0WB => x 317 } 318 } 319 320 def getVlWBPort = { 321 wbPortConfigs.collectFirst { 322 case x: VlWB => x 323 } 324 } 325 326 /** 327 * Get the [[DataConfig]] that this exu need to read 328 */ 329 def pregRdDataCfgSet: Set[DataConfig] = { 330 this.rfrPortConfigs.flatten.map(_.getDataConfig).toSet 331 } 332 333 /** 334 * Get the [[DataConfig]] that this exu need to write 335 */ 336 def pregWbDataCfgSet: Set[DataConfig] = { 337 this.wbPortConfigs.map(_.dataCfg).toSet 338 } 339 340 def getRfReadDataCfgSet: Seq[Set[DataConfig]] = { 341 val fuSrcsCfgSet: Seq[Seq[Set[DataConfig]]] = fuConfigs.map(_.getRfReadDataCfgSet) 342 val alignedFuSrcsCfgSet: Seq[Seq[Set[DataConfig]]] = fuSrcsCfgSet.map(x => x ++ Seq.fill(numRegSrc - x.length)(Set[DataConfig]())) 343 344 val exuSrcsCfgSet = alignedFuSrcsCfgSet.reduce((x, y) => (x zip y).map { case (cfg1, cfg2) => cfg1 union cfg2 }) 345 346 exuSrcsCfgSet 347 } 348 349 /** 350 * Get the [[DataConfig]] mapped indices of source data of exu 351 * 352 * @example 353 * {{{ 354 * fuCfg.srcData = Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()) 355 * getRfReadSrcIdx(VecData()) = Seq(0, 1, 2) 356 * getRfReadSrcIdx(MaskSrcData()) = Seq(3) 357 * getRfReadSrcIdx(VConfigData()) = Seq(4) 358 * }}} 359 * @return Map[DataConfig -> Seq[indices]] 360 */ 361 def getRfReadSrcIdx: Map[DataConfig, Seq[Int]] = { 362 val dataCfgs = DataConfig.RegSrcDataSet 363 val rfRdDataCfgSet = this.getRfReadDataCfgSet 364 dataCfgs.toSeq.map { cfg => 365 ( 366 cfg, 367 rfRdDataCfgSet.zipWithIndex.map { case (set, srcIdx) => 368 if (set.contains(cfg)) 369 Option(srcIdx) 370 else 371 None 372 }.filter(_.nonEmpty).map(_.get) 373 ) 374 }.toMap 375 } 376 377 def genExuModule(implicit p: Parameters): ExeUnit = { 378 new ExeUnit(this) 379 } 380 381 def genExuInputBundle(implicit p: Parameters): ExuInput = { 382 new ExuInput(this) 383 } 384 385 def genExuOutputBundle(implicit p: Parameters): ExuOutput = { 386 new ExuOutput(this) 387 } 388 389 def genExuBypassBundle(implicit p: Parameters): ExuBypassBundle = { 390 new ExuBypassBundle(this) 391 } 392} 393