1package xiangshan.backend.exu 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import xiangshan.backend.BackendParams 7import xiangshan.backend.Bundles.{ExuBypassBundle, ExuInput, ExuOutput} 8import xiangshan.backend.datapath.DataConfig.DataConfig 9import xiangshan.backend.datapath.RdConfig._ 10import xiangshan.backend.datapath.WbConfig._ 11import xiangshan.backend.datapath.{DataConfig, WakeUpConfig} 12import xiangshan.backend.fu.{FuConfig, FuType} 13import xiangshan.backend.issue.{IssueBlockParams, SchedulerType, IntScheduler, VfScheduler, MemScheduler} 14import scala.collection.mutable 15 16case class ExeUnitParams( 17 name : String, 18 fuConfigs : Seq[FuConfig], 19 wbPortConfigs : Seq[PregWB], 20 rfrPortConfigs: Seq[Seq[RdConfig]], 21 copyWakeupOut: Boolean = false, 22 copyDistance: Int = 1, 23 fakeUnit : Boolean = false, 24)( 25 implicit 26 val schdType: SchedulerType, 27) { 28 // calculated configs 29 var iqWakeUpSourcePairs: Seq[WakeUpConfig] = Seq() 30 var iqWakeUpSinkPairs: Seq[WakeUpConfig] = Seq() 31 // used in bypass to select data of exu output 32 var exuIdx: Int = -1 33 var backendParam: BackendParams = null 34 35 val numIntSrc: Int = fuConfigs.map(_.numIntSrc).max 36 val numFpSrc: Int = fuConfigs.map(_.numFpSrc).max 37 val numVecSrc: Int = fuConfigs.map(_.numVecSrc).max 38 val numVfSrc: Int = fuConfigs.map(_.numVfSrc).max 39 val numV0Src: Int = fuConfigs.map(_.numV0Src).max 40 val numVlSrc: Int = fuConfigs.map(_.numVlSrc).max 41 val numRegSrc: Int = fuConfigs.map(_.numRegSrc).max 42 val numSrc: Int = fuConfigs.map(_.numSrc).max 43 val dataBitsMax: Int = fuConfigs.map(_.dataBits).max 44 val readIntRf: Boolean = numIntSrc > 0 45 val readFpRf: Boolean = numFpSrc > 0 46 val readVecRf: Boolean = numVecSrc > 0 47 val readVfRf: Boolean = numVfSrc > 0 48 val writeIntRf: Boolean = fuConfigs.map(_.writeIntRf).reduce(_ || _) 49 val writeFpRf: Boolean = fuConfigs.map(_.writeFpRf).reduce(_ || _) 50 val writeVecRf: Boolean = fuConfigs.map(_.writeVecRf).reduce(_ || _) 51 val writeV0Rf: Boolean = fuConfigs.map(_.writeV0Rf).reduce(_ || _) 52 val writeVlRf: Boolean = fuConfigs.map(_.writeVlRf).reduce(_ || _) 53 val needIntWen: Boolean = fuConfigs.map(_.needIntWen).reduce(_ || _) 54 val needFpWen: Boolean = fuConfigs.map(_.needFpWen).reduce(_ || _) 55 val needVecWen: Boolean = fuConfigs.map(_.needVecWen).reduce(_ || _) 56 val needV0Wen: Boolean = fuConfigs.map(_.needV0Wen).reduce(_ || _) 57 val needVlWen: Boolean = fuConfigs.map(_.needVlWen).reduce(_ || _) 58 val needOg2: Boolean = fuConfigs.map(_.needOg2).reduce(_ || _) 59 val writeVfRf: Boolean = writeVecRf 60 val writeFflags: Boolean = fuConfigs.map(_.writeFflags).reduce(_ || _) 61 val writeVxsat: Boolean = fuConfigs.map(_.writeVxsat).reduce(_ || _) 62 val hasNoDataWB: Boolean = fuConfigs.map(_.hasNoDataWB).reduce(_ && _) 63 val hasRedirect: Boolean = fuConfigs.map(_.hasRedirect).reduce(_ || _) 64 val hasPredecode: Boolean = fuConfigs.map(_.hasPredecode).reduce(_ || _) 65 val exceptionOut: Seq[Int] = fuConfigs.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted 66 val hasLoadError: Boolean = fuConfigs.map(_.hasLoadError).reduce(_ || _) 67 val flushPipe: Boolean = fuConfigs.map(_.flushPipe).reduce(_ || _) 68 val replayInst: Boolean = fuConfigs.map(_.replayInst).reduce(_ || _) 69 val trigger: Boolean = fuConfigs.map(_.trigger).reduce(_ || _) 70 val needExceptionGen: Boolean = exceptionOut.nonEmpty || flushPipe || replayInst || trigger 71 val needPc: Boolean = fuConfigs.map(_.needPc).reduce(_ || _) 72 val needTarget: Boolean = fuConfigs.map(_.needTargetPc).reduce(_ || _) 73 val needPdInfo: Boolean = fuConfigs.map(_.needPdInfo).reduce(_ || _) 74 val needSrcFrm: Boolean = fuConfigs.map(_.needSrcFrm).reduce(_ || _) 75 val needSrcVxrm: Boolean = fuConfigs.map(_.needSrcVxrm).reduce(_ || _) 76 val needFPUCtrl: Boolean = fuConfigs.map(_.needFPUCtrl).reduce(_ || _) 77 val needVPUCtrl: Boolean = fuConfigs.map(_.needVecCtrl).reduce(_ || _) 78 val writeVConfig: Boolean = fuConfigs.map(_.writeVlRf).reduce(_ || _) 79 val writeVType: Boolean = fuConfigs.map(_.writeVType).reduce(_ || _) 80 val isHighestWBPriority: Boolean = wbPortConfigs.forall(_.priority == 0) 81 82 val isIntExeUnit: Boolean = schdType.isInstanceOf[IntScheduler] 83 val isVfExeUnit: Boolean = schdType.isInstanceOf[VfScheduler] 84 val isMemExeUnit: Boolean = schdType.isInstanceOf[MemScheduler] 85 86 require(needPc && needTarget || !needPc && !needTarget, "The ExeUnit must need both PC and Target PC") 87 88 def copyNum: Int = { 89 val setIQ = mutable.Set[IssueBlockParams]() 90 iqWakeUpSourcePairs.map(_.sink).foreach{ wakeupSink => 91 backendParam.allIssueParams.map{ issueParams => 92 if (issueParams.exuBlockParams.contains(wakeupSink.getExuParam(backendParam.allExuParams))) { 93 setIQ.add(issueParams) 94 } 95 } 96 } 97 println(s"[Backend] exuIdx ${exuIdx} numWakeupIQ ${setIQ.size}") 98 1 + setIQ.size / copyDistance 99 } 100 def rdPregIdxWidth: Int = { 101 this.pregRdDataCfgSet.map(dataCfg => backendParam.getPregParams(dataCfg).addrWidth).fold(0)(_ max _) 102 } 103 104 def wbPregIdxWidth: Int = { 105 this.pregWbDataCfgSet.map(dataCfg => backendParam.getPregParams(dataCfg).addrWidth).fold(0)(_ max _) 106 } 107 108 val writeIntFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeIntRf) 109 val writeFpFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeFpRf) 110 val writeVfFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeVecRf) 111 val writeV0FuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeV0Rf) 112 val writeVlFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeVlRf) 113 114 /** 115 * Check if this exu has certain latency 116 */ 117 def latencyCertain: Boolean = fuConfigs.map(x => x.latency.latencyVal.nonEmpty).reduce(_ && _) 118 def intLatencyCertain: Boolean = writeIntFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 119 def fpLatencyCertain: Boolean = writeFpFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 120 def vfLatencyCertain: Boolean = writeVfFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 121 def v0LatencyCertain: Boolean = writeV0FuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 122 def vlLatencyCertain: Boolean = writeVlFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 123 // only load use it 124 def hasUncertainLatencyVal: Boolean = fuConfigs.map(x => x.latency.uncertainLatencyVal.nonEmpty).reduce(_ || _) 125 126 /** 127 * Get mapping from FuType to Latency value. 128 * If both [[latencyCertain]] and [[hasUncertainLatencyVal]] are false, get empty [[Map]] 129 * 130 * @return Map[ [[BigInt]], Latency] 131 */ 132 def fuLatencyMap: Map[FuType.OHType, Int] = { 133 if (latencyCertain) 134 if(needOg2) fuConfigs.map(x => (x.fuType, x.latency.latencyVal.get + 1)).toMap else fuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 135 else if (hasUncertainLatencyVal) 136 fuConfigs.map(x => (x.fuType, x.latency.uncertainLatencyVal)).toMap.filter(_._2.nonEmpty).map(x => (x._1, x._2.get)) 137 else 138 Map() 139 } 140 def wakeUpFuLatencyMap: Map[FuType.OHType, Int] = { 141 if (latencyCertain) 142 fuConfigs.filterNot(_.hasNoDataWB).map(x => (x.fuType, x.latency.latencyVal.get)).toMap 143 else if (hasUncertainLatencyVal) 144 fuConfigs.filterNot(_.hasNoDataWB).map(x => (x.fuType, x.latency.uncertainLatencyVal.get)).toMap 145 else 146 Map() 147 } 148 149 /** 150 * Get set of latency of function units. 151 * If both [[latencyCertain]] and [[hasUncertainLatencyVal]] are false, get empty [[Set]] 152 * 153 * @return Set[Latency] 154 */ 155 def fuLatancySet: Set[Int] = fuLatencyMap.values.toSet 156 157 def wakeUpFuLatancySet: Set[Int] = wakeUpFuLatencyMap.values.toSet 158 159 def latencyValMax: Int = fuLatancySet.fold(0)(_ max _) 160 161 def intFuLatencyMap: Map[FuType.OHType, Int] = { 162 if (intLatencyCertain) { 163 if (isVfExeUnit) { 164 // vf exe unit writing back to int regfile should delay 1 cycle 165 // vf exe unit need og2 --> delay 1 cycle 166 writeIntFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get + 2)).toMap 167 } else { 168 writeIntFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 169 } 170 } 171 else 172 Map() 173 } 174 175 def intLatencyValMax: Int = intFuLatencyMap.values.fold(0)(_ max _) 176 177 def fpFuLatencyMap: Map[FuType.OHType, Int] = { 178 if (fpLatencyCertain) 179 writeFpFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 180 else 181 Map() 182 } 183 184 def fpLatencyValMax: Int = fpFuLatencyMap.values.fold(0)(_ max _) 185 186 def vfFuLatencyMap: Map[FuType.OHType, Int] = { 187 if (vfLatencyCertain) 188 if(needOg2) writeVfFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get + 1)).toMap else writeVfFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 189 else 190 Map() 191 } 192 193 def vfLatencyValMax: Int = vfFuLatencyMap.values.fold(0)(_ max _) 194 195 def v0FuLatencyMap: Map[FuType.OHType, Int] = { 196 if (v0LatencyCertain) 197 if(needOg2) writeV0FuConfigs.map(x => (x.fuType, x.latency.latencyVal.get + 1)).toMap else writeV0FuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 198 else 199 Map() 200 } 201 202 def v0LatencyValMax: Int = v0FuLatencyMap.values.fold(0)(_ max _) 203 204 def vlFuLatencyMap: Map[FuType.OHType, Int] = { 205 if (vlLatencyCertain) 206 if(needOg2) writeVlFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get + 1)).toMap else writeVlFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 207 else 208 Map() 209 } 210 211 def vlLatencyValMax: Int = vlFuLatencyMap.values.fold(0)(_ max _) 212 213 /** 214 * Check if this exu has fixed latency 215 */ 216 def isFixedLatency: Boolean = { 217 if (latencyCertain) 218 return fuConfigs.map(x => x.latency.latencyVal.get == fuConfigs.head.latency.latencyVal.get).reduce(_ && _) 219 false 220 } 221 222 def hasCSR: Boolean = fuConfigs.map(_.isCsr).reduce(_ || _) 223 224 def hasFence: Boolean = fuConfigs.map(_.isFence).reduce(_ || _) 225 226 def hasBrhFu = fuConfigs.map(_.fuType == FuType.brh).reduce(_ || _) 227 228 def hasJmpFu = fuConfigs.map(_.fuType == FuType.jmp).reduce(_ || _) 229 230 def hasLoadFu = fuConfigs.map(_.name == "ldu").reduce(_ || _) 231 232 def hasVLoadFu = fuConfigs.map(_.fuType == FuType.vldu).reduce(_ || _) 233 234 def hasVStoreFu = fuConfigs.map(_.fuType == FuType.vstu).reduce(_ || _) 235 236 def hasVecLsFu = fuConfigs.map(x => FuType.FuTypeOrR(x.fuType, Seq(FuType.vldu, FuType.vstu))).reduce(_ || _) 237 238 def hasStoreAddrFu = fuConfigs.map(_.name == "sta").reduce(_ || _) 239 240 def hasStdFu = fuConfigs.map(_.name == "std").reduce(_ || _) 241 242 def hasMemAddrFu = hasLoadFu || hasStoreAddrFu || hasVLoadFu || hasHyldaFu || hasHystaFu || hasVLoadFu || hasVStoreFu 243 244 def hasHyldaFu = fuConfigs.map(_.name == "hylda").reduce(_ || _) 245 246 def hasHystaFu = fuConfigs.map(_.name == "hysta").reduce(_ || _) 247 248 def hasLoadExu = hasLoadFu || hasHyldaFu 249 250 def hasStoreAddrExu = hasStoreAddrFu || hasHystaFu 251 252 def hasVecFu = fuConfigs.map(x => FuConfig.VecArithFuConfigs.contains(x)).reduce(_ || _) 253 254 def getSrcDataType(srcIdx: Int): Set[DataConfig] = { 255 fuConfigs.map(_.getSrcDataType(srcIdx)).reduce(_ ++ _) 256 } 257 258 def immType: Set[UInt] = fuConfigs.map(x => x.immType).reduce(_ ++ _) 259 260 def getWBSource: SchedulerType = { 261 schdType 262 } 263 264 def hasCrossWb: Boolean = { 265 schdType match { 266 case IntScheduler() => writeFpRf || writeVecRf 267 case VfScheduler() => writeIntRf 268 case _ => false 269 } 270 } 271 272 def canAccept(fuType: UInt): Bool = { 273 Cat(fuConfigs.map(_.fuType.U === fuType)).orR 274 } 275 276 def hasUncertainLatency: Boolean = fuConfigs.map(_.latency.latencyVal.isEmpty).reduce(_ || _) 277 278 def bindBackendParam(param: BackendParams): Unit = { 279 backendParam = param 280 } 281 282 def updateIQWakeUpConfigs(cfgs: Seq[WakeUpConfig]) = { 283 this.iqWakeUpSourcePairs = cfgs.filter(_.source.name == this.name) 284 this.iqWakeUpSinkPairs = cfgs.filter(_.sink.name == this.name) 285 if (this.isIQWakeUpSource) { 286 require(!this.hasUncertainLatency || hasLoadFu || hasHyldaFu, s"${this.name} is a not-LDU IQ wake up source , but has UncertainLatency") 287 } 288 } 289 290 def updateExuIdx(idx: Int): Unit = { 291 this.exuIdx = idx 292 } 293 294 def isIQWakeUpSource = this.iqWakeUpSourcePairs.nonEmpty 295 296 def isIQWakeUpSink = this.iqWakeUpSinkPairs.nonEmpty 297 298 def getIntWBPort = { 299 wbPortConfigs.collectFirst { 300 case x: IntWB => x 301 } 302 } 303 304 def getFpWBPort = { 305 wbPortConfigs.collectFirst { 306 case x: FpWB => x 307 } 308 } 309 310 def getVfWBPort = { 311 wbPortConfigs.collectFirst { 312 case x: VfWB => x 313 } 314 } 315 316 def getV0WBPort = { 317 wbPortConfigs.collectFirst { 318 case x: V0WB => x 319 } 320 } 321 322 def getVlWBPort = { 323 wbPortConfigs.collectFirst { 324 case x: VlWB => x 325 } 326 } 327 328 /** 329 * Get the [[DataConfig]] that this exu need to read 330 */ 331 def pregRdDataCfgSet: Set[DataConfig] = { 332 this.rfrPortConfigs.flatten.map(_.getDataConfig).toSet 333 } 334 335 /** 336 * Get the [[DataConfig]] that this exu need to write 337 */ 338 def pregWbDataCfgSet: Set[DataConfig] = { 339 this.wbPortConfigs.map(_.dataCfg).toSet 340 } 341 342 def getRfReadDataCfgSet: Seq[Set[DataConfig]] = { 343 val fuSrcsCfgSet: Seq[Seq[Set[DataConfig]]] = fuConfigs.map(_.getRfReadDataCfgSet) 344 val alignedFuSrcsCfgSet: Seq[Seq[Set[DataConfig]]] = fuSrcsCfgSet.map(x => x ++ Seq.fill(numRegSrc - x.length)(Set[DataConfig]())) 345 346 val exuSrcsCfgSet = alignedFuSrcsCfgSet.reduce((x, y) => (x zip y).map { case (cfg1, cfg2) => cfg1 union cfg2 }) 347 348 exuSrcsCfgSet 349 } 350 351 /** 352 * Get the [[DataConfig]] mapped indices of source data of exu 353 * 354 * @example 355 * {{{ 356 * fuCfg.srcData = Seq(VecData(), VecData(), VecData(), V0Data(), VlData()) 357 * getRfReadSrcIdx(VecData()) = Seq(0, 1, 2) 358 * getRfReadSrcIdx(V0Data()) = Seq(3) 359 * getRfReadSrcIdx(VlData()) = Seq(4) 360 * }}} 361 * @return Map[DataConfig -> Seq[indices]] 362 */ 363 def getRfReadSrcIdx: Map[DataConfig, Seq[Int]] = { 364 val dataCfgs = DataConfig.RegSrcDataSet 365 val rfRdDataCfgSet = this.getRfReadDataCfgSet 366 dataCfgs.toSeq.map { cfg => 367 ( 368 cfg, 369 rfRdDataCfgSet.zipWithIndex.map { case (set, srcIdx) => 370 if (set.contains(cfg)) 371 Option(srcIdx) 372 else 373 None 374 }.filter(_.nonEmpty).map(_.get) 375 ) 376 }.toMap 377 } 378 379 def genExuModule(implicit p: Parameters): ExeUnit = { 380 new ExeUnit(this) 381 } 382 383 def genExuInputBundle(implicit p: Parameters): ExuInput = { 384 new ExuInput(this) 385 } 386 387 def genExuOutputBundle(implicit p: Parameters): ExuOutput = { 388 new ExuOutput(this) 389 } 390 391 def genExuBypassBundle(implicit p: Parameters): ExuBypassBundle = { 392 new ExuBypassBundle(this) 393 } 394} 395