1package xiangshan.backend.exu 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import xiangshan.backend.BackendParams 7import xiangshan.backend.Bundles.{ExuBypassBundle, ExuInput, ExuOutput} 8import xiangshan.backend.datapath.DataConfig.DataConfig 9import xiangshan.backend.datapath.RdConfig._ 10import xiangshan.backend.datapath.WbConfig.{IntWB, PregWB, VfWB} 11import xiangshan.backend.datapath.{DataConfig, WakeUpConfig} 12import xiangshan.backend.fu.{FuConfig, FuType} 13import xiangshan.backend.issue.{IssueBlockParams, SchedulerType, IntScheduler, VfScheduler, MemScheduler} 14import scala.collection.mutable 15 16case class ExeUnitParams( 17 name : String, 18 fuConfigs : Seq[FuConfig], 19 wbPortConfigs : Seq[PregWB], 20 rfrPortConfigs: Seq[Seq[RdConfig]], 21 copyWakeupOut: Boolean = false, 22 copyDistance: Int = 1, 23 fakeUnit : Boolean = false, 24)( 25 implicit 26 val schdType: SchedulerType, 27) { 28 // calculated configs 29 var iqWakeUpSourcePairs: Seq[WakeUpConfig] = Seq() 30 var iqWakeUpSinkPairs: Seq[WakeUpConfig] = Seq() 31 // used in bypass to select data of exu output 32 var exuIdx: Int = -1 33 var backendParam: BackendParams = null 34 35 val numIntSrc: Int = fuConfigs.map(_.numIntSrc).max 36 val numFpSrc: Int = fuConfigs.map(_.numFpSrc).max 37 val numVecSrc: Int = fuConfigs.map(_.numVecSrc).max 38 val numVfSrc: Int = fuConfigs.map(_.numVfSrc).max 39 val numRegSrc: Int = fuConfigs.map(_.numRegSrc).max 40 val numSrc: Int = fuConfigs.map(_.numSrc).max 41 val dataBitsMax: Int = fuConfigs.map(_.dataBits).max 42 val readIntRf: Boolean = numIntSrc > 0 43 val readFpRf: Boolean = numFpSrc > 0 44 val readVecRf: Boolean = numVecSrc > 0 45 val readVfRf: Boolean = numVfSrc > 0 46 val writeIntRf: Boolean = fuConfigs.map(_.writeIntRf).reduce(_ || _) 47 val writeFpRf: Boolean = fuConfigs.map(_.writeFpRf).reduce(_ || _) 48 val writeVecRf: Boolean = fuConfigs.map(_.writeVecRf).reduce(_ || _) 49 val needIntWen: Boolean = fuConfigs.map(_.needIntWen).reduce(_ || _) 50 val needFpWen: Boolean = fuConfigs.map(_.needFpWen).reduce(_ || _) 51 val needVecWen: Boolean = fuConfigs.map(_.needVecWen).reduce(_ || _) 52 val needOg2: Boolean = fuConfigs.map(_.needOg2).reduce(_ || _) 53 val writeVfRf: Boolean = writeFpRf || writeVecRf 54 val writeFflags: Boolean = fuConfigs.map(_.writeFflags).reduce(_ || _) 55 val writeVxsat: Boolean = fuConfigs.map(_.writeVxsat).reduce(_ || _) 56 val hasNoDataWB: Boolean = fuConfigs.map(_.hasNoDataWB).reduce(_ && _) 57 val hasRedirect: Boolean = fuConfigs.map(_.hasRedirect).reduce(_ || _) 58 val hasPredecode: Boolean = fuConfigs.map(_.hasPredecode).reduce(_ || _) 59 val exceptionOut: Seq[Int] = fuConfigs.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted 60 val hasLoadError: Boolean = fuConfigs.map(_.hasLoadError).reduce(_ || _) 61 val flushPipe: Boolean = fuConfigs.map(_.flushPipe).reduce(_ || _) 62 val replayInst: Boolean = fuConfigs.map(_.replayInst).reduce(_ || _) 63 val trigger: Boolean = fuConfigs.map(_.trigger).reduce(_ || _) 64 val needExceptionGen: Boolean = exceptionOut.nonEmpty || flushPipe || replayInst || trigger 65 val needPc: Boolean = fuConfigs.map(_.needPc).reduce(_ || _) 66 val needTarget: Boolean = fuConfigs.map(_.needTargetPc).reduce(_ || _) 67 val needPdInfo: Boolean = fuConfigs.map(_.needPdInfo).reduce(_ || _) 68 val needSrcFrm: Boolean = fuConfigs.map(_.needSrcFrm).reduce(_ || _) 69 val needSrcVxrm: Boolean = fuConfigs.map(_.needSrcVxrm).reduce(_ || _) 70 val needFPUCtrl: Boolean = fuConfigs.map(_.needFPUCtrl).reduce(_ || _) 71 val needVPUCtrl: Boolean = fuConfigs.map(_.needVecCtrl).reduce(_ || _) 72 val isHighestWBPriority: Boolean = wbPortConfigs.forall(_.priority == 0) 73 74 val isIntExeUnit: Boolean = schdType.isInstanceOf[IntScheduler] 75 val isVfExeUnit: Boolean = schdType.isInstanceOf[VfScheduler] 76 val isMemExeUnit: Boolean = schdType.isInstanceOf[MemScheduler] 77 78 require(needPc && needTarget || !needPc && !needTarget, "The ExeUnit must need both PC and Target PC") 79 80 def copyNum: Int = { 81 val setIQ = mutable.Set[IssueBlockParams]() 82 iqWakeUpSourcePairs.map(_.sink).foreach{ wakeupSink => 83 backendParam.allIssueParams.map{ issueParams => 84 if (issueParams.exuBlockParams.contains(wakeupSink.getExuParam(backendParam.allExuParams))) { 85 setIQ.add(issueParams) 86 } 87 } 88 } 89 println(s"[Backend] exuIdx ${exuIdx} numWakeupIQ ${setIQ.size}") 90 1 + setIQ.size / copyDistance 91 } 92 def rdPregIdxWidth: Int = { 93 this.pregRdDataCfgSet.map(dataCfg => backendParam.getPregParams(dataCfg).addrWidth).fold(0)(_ max _) 94 } 95 96 def wbPregIdxWidth: Int = { 97 this.pregWbDataCfgSet.map(dataCfg => backendParam.getPregParams(dataCfg).addrWidth).fold(0)(_ max _) 98 } 99 100 val writeIntFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeIntRf) 101 val writeVfFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeFpRf || x.writeVecRf) 102 103 /** 104 * Check if this exu has certain latency 105 */ 106 def latencyCertain: Boolean = fuConfigs.map(x => x.latency.latencyVal.nonEmpty).reduce(_ && _) 107 def intLatencyCertain: Boolean = writeIntFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 108 def vfLatencyCertain: Boolean = writeVfFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 109 // only load use it 110 def hasUncertainLatencyVal: Boolean = fuConfigs.map(x => x.latency.uncertainLatencyVal.nonEmpty).reduce(_ || _) 111 112 /** 113 * Get mapping from FuType to Latency value. 114 * If both [[latencyCertain]] and [[hasUncertainLatencyVal]] are false, get empty [[Map]] 115 * 116 * @return Map[ [[BigInt]], Latency] 117 */ 118 def fuLatencyMap: Map[FuType.OHType, Int] = { 119 if (latencyCertain) 120 if(needOg2) fuConfigs.map(x => (x.fuType, x.latency.latencyVal.get + 1)).toMap else fuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 121 else if (hasUncertainLatencyVal) 122 fuConfigs.map(x => (x.fuType, x.latency.uncertainLatencyVal)).toMap.filter(_._2.nonEmpty).map(x => (x._1, x._2.get)) 123 else 124 Map() 125 } 126 def wakeUpFuLatencyMap: Map[FuType.OHType, Int] = { 127 if (latencyCertain) 128 fuConfigs.filterNot(_.hasNoDataWB).map(x => (x.fuType, x.latency.latencyVal.get)).toMap 129 else if (hasUncertainLatencyVal) 130 fuConfigs.filterNot(_.hasNoDataWB).map(x => (x.fuType, x.latency.uncertainLatencyVal.get)).toMap 131 else 132 Map() 133 } 134 135 /** 136 * Get set of latency of function units. 137 * If both [[latencyCertain]] and [[hasUncertainLatencyVal]] are false, get empty [[Set]] 138 * 139 * @return Set[Latency] 140 */ 141 def fuLatancySet: Set[Int] = fuLatencyMap.values.toSet 142 143 def wakeUpFuLatancySet: Set[Int] = wakeUpFuLatencyMap.values.toSet 144 145 def latencyValMax: Int = fuLatancySet.fold(0)(_ max _) 146 147 def intFuLatencyMap: Map[FuType.OHType, Int] = { 148 if (intLatencyCertain) { 149 if (isVfExeUnit) { 150 // vf exe unit writing back to int regfile should delay 1 cycle 151 // vf exe unit need og2 --> delay 1 cycle 152 writeIntFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get + 2)).toMap 153 } else { 154 writeIntFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 155 } 156 } 157 else 158 Map() 159 } 160 161 def intLatencyValMax: Int = intFuLatencyMap.values.fold(0)(_ max _) 162 163 def vfFuLatencyMap: Map[FuType.OHType, Int] = { 164 if (vfLatencyCertain) 165 if(needOg2) writeVfFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get + 1)).toMap else writeVfFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 166 else 167 Map() 168 } 169 170 def vfLatencyValMax: Int = vfFuLatencyMap.values.fold(0)(_ max _) 171 172 /** 173 * Check if this exu has fixed latency 174 */ 175 def isFixedLatency: Boolean = { 176 if (latencyCertain) 177 return fuConfigs.map(x => x.latency.latencyVal.get == fuConfigs.head.latency.latencyVal.get).reduce(_ && _) 178 false 179 } 180 181 def hasCSR: Boolean = fuConfigs.map(_.isCsr).reduce(_ || _) 182 183 def hasFence: Boolean = fuConfigs.map(_.isFence).reduce(_ || _) 184 185 def hasBrhFu = fuConfigs.map(_.fuType == FuType.brh).reduce(_ || _) 186 187 def hasJmpFu = fuConfigs.map(_.fuType == FuType.jmp).reduce(_ || _) 188 189 def hasLoadFu = fuConfigs.map(_.name == "ldu").reduce(_ || _) 190 191 def hasVLoadFu = fuConfigs.map(_.fuType == FuType.vldu).reduce(_ || _) 192 193 def hasVStoreFu = fuConfigs.map(_.fuType == FuType.vstu).reduce(_ || _) 194 195 def hasStoreAddrFu = fuConfigs.map(_.name == "sta").reduce(_ || _) 196 197 def hasStdFu = fuConfigs.map(_.name == "std").reduce(_ || _) 198 199 def hasMemAddrFu = hasLoadFu || hasStoreAddrFu || hasVLoadFu || hasHyldaFu || hasHystaFu || hasVLoadFu || hasVStoreFu 200 201 def hasHyldaFu = fuConfigs.map(_.name == "hylda").reduce(_ || _) 202 203 def hasHystaFu = fuConfigs.map(_.name == "hysta").reduce(_ || _) 204 205 def hasLoadExu = hasLoadFu || hasHyldaFu 206 207 def hasStoreAddrExu = hasStoreAddrFu || hasHystaFu 208 209 def hasVecFu = fuConfigs.map(x => FuConfig.VecArithFuConfigs.contains(x)).reduce(_ || _) 210 211 def getSrcDataType(srcIdx: Int): Set[DataConfig] = { 212 fuConfigs.map(_.getSrcDataType(srcIdx)).reduce(_ ++ _) 213 } 214 215 def immType: Set[UInt] = fuConfigs.map(x => x.immType).reduce(_ ++ _) 216 217 def getWBSource: SchedulerType = { 218 schdType 219 } 220 221 def hasCrossWb: Boolean = { 222 schdType match { 223 case IntScheduler() => writeFpRf || writeVecRf 224 case VfScheduler() => writeIntRf 225 case _ => false 226 } 227 } 228 229 def canAccept(fuType: UInt): Bool = { 230 Cat(fuConfigs.map(_.fuType.U === fuType)).orR 231 } 232 233 def hasUncertainLatency: Boolean = fuConfigs.map(_.latency.latencyVal.isEmpty).reduce(_ || _) 234 235 def bindBackendParam(param: BackendParams): Unit = { 236 backendParam = param 237 } 238 239 def updateIQWakeUpConfigs(cfgs: Seq[WakeUpConfig]) = { 240 this.iqWakeUpSourcePairs = cfgs.filter(_.source.name == this.name) 241 this.iqWakeUpSinkPairs = cfgs.filter(_.sink.name == this.name) 242 if (this.isIQWakeUpSource) { 243 require(!this.hasUncertainLatency || hasLoadFu || hasHyldaFu, s"${this.name} is a not-LDU IQ wake up source , but has UncertainLatency") 244 } 245 } 246 247 def updateExuIdx(idx: Int): Unit = { 248 this.exuIdx = idx 249 } 250 251 def isIQWakeUpSource = this.iqWakeUpSourcePairs.nonEmpty 252 253 def isIQWakeUpSink = this.iqWakeUpSinkPairs.nonEmpty 254 255 def getIntWBPort = { 256 wbPortConfigs.collectFirst { 257 case x: IntWB => x 258 } 259 } 260 261 def getVfWBPort = { 262 wbPortConfigs.collectFirst { 263 case x: VfWB => x 264 } 265 } 266 267 /** 268 * Get the [[DataConfig]] that this exu need to read 269 */ 270 def pregRdDataCfgSet: Set[DataConfig] = { 271 this.rfrPortConfigs.flatten.map(_.getDataConfig).toSet 272 } 273 274 /** 275 * Get the [[DataConfig]] that this exu need to write 276 */ 277 def pregWbDataCfgSet: Set[DataConfig] = { 278 this.wbPortConfigs.map(_.dataCfg).toSet 279 } 280 281 def getRfReadDataCfgSet: Seq[Set[DataConfig]] = { 282 val fuSrcsCfgSet: Seq[Seq[Set[DataConfig]]] = fuConfigs.map(_.getRfReadDataCfgSet) 283 val alignedFuSrcsCfgSet: Seq[Seq[Set[DataConfig]]] = fuSrcsCfgSet.map(x => x ++ Seq.fill(numRegSrc - x.length)(Set[DataConfig]())) 284 285 val exuSrcsCfgSet = alignedFuSrcsCfgSet.reduce((x, y) => (x zip y).map { case (cfg1, cfg2) => cfg1 union cfg2 }) 286 287 exuSrcsCfgSet 288 } 289 290 /** 291 * Get the [[DataConfig]] mapped indices of source data of exu 292 * 293 * @example 294 * {{{ 295 * fuCfg.srcData = Seq(VecData(), VecData(), VecData(), MaskSrcData(), VConfigData()) 296 * getRfReadSrcIdx(VecData()) = Seq(0, 1, 2) 297 * getRfReadSrcIdx(MaskSrcData()) = Seq(3) 298 * getRfReadSrcIdx(VConfigData()) = Seq(4) 299 * }}} 300 * @return Map[DataConfig -> Seq[indices]] 301 */ 302 def getRfReadSrcIdx: Map[DataConfig, Seq[Int]] = { 303 val dataCfgs = DataConfig.RegSrcDataSet 304 val rfRdDataCfgSet = this.getRfReadDataCfgSet 305 dataCfgs.toSeq.map { cfg => 306 ( 307 cfg, 308 rfRdDataCfgSet.zipWithIndex.map { case (set, srcIdx) => 309 if (set.contains(cfg)) 310 Option(srcIdx) 311 else 312 None 313 }.filter(_.nonEmpty).map(_.get) 314 ) 315 }.toMap 316 } 317 318 def genExuModule(implicit p: Parameters): ExeUnit = { 319 new ExeUnit(this) 320 } 321 322 def genExuInputBundle(implicit p: Parameters): ExuInput = { 323 new ExuInput(this) 324 } 325 326 def genExuOutputBundle(implicit p: Parameters): ExuOutput = { 327 new ExuOutput(this) 328 } 329 330 def genExuBypassBundle(implicit p: Parameters): ExuBypassBundle = { 331 new ExuBypassBundle(this) 332 } 333} 334