1package xiangshan.backend.exu 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import xiangshan.backend.BackendParams 7import xiangshan.backend.Bundles.{ExuBypassBundle, ExuInput, ExuOutput} 8import xiangshan.backend.datapath.DataConfig.DataConfig 9import xiangshan.backend.datapath.RdConfig._ 10import xiangshan.backend.datapath.WbConfig._ 11import xiangshan.backend.datapath.{DataConfig, WakeUpConfig} 12import xiangshan.backend.fu.{FuConfig, FuType} 13import xiangshan.backend.issue.{IssueBlockParams, SchedulerType, IntScheduler, VfScheduler, MemScheduler} 14import scala.collection.mutable 15 16case class ExeUnitParams( 17 name : String, 18 fuConfigs : Seq[FuConfig], 19 wbPortConfigs : Seq[PregWB], 20 rfrPortConfigs: Seq[Seq[RdConfig]], 21 copyWakeupOut: Boolean = false, 22 copyDistance: Int = 1, 23 fakeUnit : Boolean = false, 24)( 25 implicit 26 val schdType: SchedulerType, 27) { 28 // calculated configs 29 var iqWakeUpSourcePairs: Seq[WakeUpConfig] = Seq() 30 var iqWakeUpSinkPairs: Seq[WakeUpConfig] = Seq() 31 // used in bypass to select data of exu output 32 var exuIdx: Int = -1 33 var backendParam: BackendParams = null 34 35 val numIntSrc: Int = fuConfigs.map(_.numIntSrc).max 36 val numFpSrc: Int = fuConfigs.map(_.numFpSrc).max 37 val numVecSrc: Int = fuConfigs.map(_.numVecSrc).max 38 val numVfSrc: Int = fuConfigs.map(_.numVfSrc).max 39 val numV0Src: Int = fuConfigs.map(_.numV0Src).max 40 val numVlSrc: Int = fuConfigs.map(_.numVlSrc).max 41 val numRegSrc: Int = fuConfigs.map(_.numRegSrc).max 42 val numSrc: Int = fuConfigs.map(_.numSrc).max 43 val destDataBitsMax: Int = fuConfigs.map(_.destDataBits).max 44 val srcDataBitsMax: Int = fuConfigs.map(x => x.srcDataBits.getOrElse(x.destDataBits)).max 45 val readIntRf: Boolean = numIntSrc > 0 46 val readFpRf: Boolean = numFpSrc > 0 47 val readVecRf: Boolean = numVecSrc > 0 48 val readVfRf: Boolean = numVfSrc > 0 49 val writeIntRf: Boolean = fuConfigs.map(_.writeIntRf).reduce(_ || _) 50 val writeFpRf: Boolean = fuConfigs.map(_.writeFpRf).reduce(_ || _) 51 val writeVecRf: Boolean = fuConfigs.map(_.writeVecRf).reduce(_ || _) 52 val writeV0Rf: Boolean = fuConfigs.map(_.writeV0Rf).reduce(_ || _) 53 val writeVlRf: Boolean = fuConfigs.map(_.writeVlRf).reduce(_ || _) 54 val needIntWen: Boolean = fuConfigs.map(_.needIntWen).reduce(_ || _) 55 val needFpWen: Boolean = fuConfigs.map(_.needFpWen).reduce(_ || _) 56 val needVecWen: Boolean = fuConfigs.map(_.needVecWen).reduce(_ || _) 57 val needV0Wen: Boolean = fuConfigs.map(_.needV0Wen).reduce(_ || _) 58 val needVlWen: Boolean = fuConfigs.map(_.needVlWen).reduce(_ || _) 59 val needOg2: Boolean = fuConfigs.map(_.needOg2).reduce(_ || _) 60 val writeVfRf: Boolean = writeVecRf 61 val writeFflags: Boolean = fuConfigs.map(_.writeFflags).reduce(_ || _) 62 val writeVxsat: Boolean = fuConfigs.map(_.writeVxsat).reduce(_ || _) 63 val hasNoDataWB: Boolean = fuConfigs.map(_.hasNoDataWB).reduce(_ && _) 64 val hasRedirect: Boolean = fuConfigs.map(_.hasRedirect).reduce(_ || _) 65 val hasPredecode: Boolean = fuConfigs.map(_.hasPredecode).reduce(_ || _) 66 val exceptionOut: Seq[Int] = fuConfigs.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted 67 val hasLoadError: Boolean = fuConfigs.map(_.hasLoadError).reduce(_ || _) 68 val flushPipe: Boolean = fuConfigs.map(_.flushPipe).reduce(_ || _) 69 val replayInst: Boolean = fuConfigs.map(_.replayInst).reduce(_ || _) 70 val trigger: Boolean = fuConfigs.map(_.trigger).reduce(_ || _) 71 val needExceptionGen: Boolean = exceptionOut.nonEmpty || flushPipe || replayInst || trigger 72 val needPc: Boolean = fuConfigs.map(_.needPc).reduce(_ || _) 73 val needTarget: Boolean = fuConfigs.map(_.needTargetPc).reduce(_ || _) 74 val needPdInfo: Boolean = fuConfigs.map(_.needPdInfo).reduce(_ || _) 75 val needSrcFrm: Boolean = fuConfigs.map(_.needSrcFrm).reduce(_ || _) 76 val needSrcVxrm: Boolean = fuConfigs.map(_.needSrcVxrm).reduce(_ || _) 77 val needFPUCtrl: Boolean = fuConfigs.map(_.needFPUCtrl).reduce(_ || _) 78 val needVPUCtrl: Boolean = fuConfigs.map(_.needVecCtrl).reduce(_ || _) 79 val writeVConfig: Boolean = fuConfigs.map(_.writeVlRf).reduce(_ || _) 80 val writeVType: Boolean = fuConfigs.map(_.writeVType).reduce(_ || _) 81 val isHighestWBPriority: Boolean = wbPortConfigs.forall(_.priority == 0) 82 83 val isIntExeUnit: Boolean = schdType.isInstanceOf[IntScheduler] 84 val isVfExeUnit: Boolean = schdType.isInstanceOf[VfScheduler] 85 val isMemExeUnit: Boolean = schdType.isInstanceOf[MemScheduler] 86 87 def needReadRegCache: Boolean = isIntExeUnit || isMemExeUnit && readIntRf 88 def needWriteRegCache: Boolean = isIntExeUnit && isIQWakeUpSource || isMemExeUnit && isIQWakeUpSource && readIntRf 89 90 // exu writeback: 0 normalout; 1 intout; 2 fpout; 3 vecout 91 val wbNeedIntWen : Boolean = writeIntRf && !isMemExeUnit 92 val wbNeedFpWen : Boolean = writeFpRf && !isMemExeUnit 93 val wbNeedVecWen : Boolean = writeVecRf && !isMemExeUnit 94 val wbNeedV0Wen : Boolean = writeV0Rf && !isMemExeUnit 95 val wbNeedVlWen : Boolean = writeVlRf && !isMemExeUnit 96 val wbPathNum: Int = Seq(wbNeedIntWen, wbNeedFpWen, wbNeedVecWen, wbNeedV0Wen, wbNeedVlWen).count(_ == true) + 1 97 val wbNeeds = Seq( 98 ("int", wbNeedIntWen), 99 ("fp", wbNeedFpWen), 100 ("vec", wbNeedVecWen), 101 ("v0", wbNeedV0Wen), 102 ("vl", wbNeedVlWen) 103 ) 104 val wbIndexeds = wbNeeds.filter(_._2).zipWithIndex.map { 105 case ((label, _), index) => (label, index + 1) 106 }.toMap 107 val wbIntIndex: Int = wbIndexeds.getOrElse("int", 0) 108 val wbFpIndex : Int = wbIndexeds.getOrElse("fp", 0) 109 val wbVecIndex: Int = wbIndexeds.getOrElse("vec", 0) 110 val wbV0Index : Int = wbIndexeds.getOrElse("v0" , 0) 111 val wbVlIndex : Int = wbIndexeds.getOrElse("vl" , 0) 112 val wbIndex: Seq[Int] = Seq(wbIntIndex, wbFpIndex, wbVecIndex, wbV0Index, wbVlIndex) 113 114 115 116 require(needPc && needTarget || !needPc && !needTarget, "The ExeUnit must need both PC and Target PC") 117 118 def copyNum: Int = { 119 val setIQ = mutable.Set[IssueBlockParams]() 120 iqWakeUpSourcePairs.map(_.sink).foreach{ wakeupSink => 121 backendParam.allIssueParams.map{ issueParams => 122 if (issueParams.exuBlockParams.contains(wakeupSink.getExuParam(backendParam.allExuParams))) { 123 setIQ.add(issueParams) 124 } 125 } 126 } 127 println(s"[Backend] exuIdx ${exuIdx} numWakeupIQ ${setIQ.size}") 128 1 + setIQ.size / copyDistance 129 } 130 def rdPregIdxWidth: Int = { 131 this.pregRdDataCfgSet.map(dataCfg => backendParam.getPregParams(dataCfg).addrWidth).fold(0)(_ max _) 132 } 133 134 def wbPregIdxWidth: Int = { 135 this.pregWbDataCfgSet.map(dataCfg => backendParam.getPregParams(dataCfg).addrWidth).fold(0)(_ max _) 136 } 137 138 val writeIntFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeIntRf) 139 val writeFpFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeFpRf) 140 val writeVfFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeVecRf) 141 val writeV0FuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeV0Rf) 142 val writeVlFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeVlRf) 143 144 /** 145 * Check if this exu has certain latency 146 */ 147 def latencyCertain: Boolean = fuConfigs.map(x => x.latency.latencyVal.nonEmpty).reduce(_ && _) 148 def intLatencyCertain: Boolean = writeIntFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 149 def fpLatencyCertain: Boolean = writeFpFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 150 def vfLatencyCertain: Boolean = writeVfFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 151 def v0LatencyCertain: Boolean = writeV0FuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 152 def vlLatencyCertain: Boolean = writeVlFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 153 // only load use it 154 def hasUncertainLatencyVal: Boolean = fuConfigs.map(x => x.latency.uncertainLatencyVal.nonEmpty).reduce(_ || _) 155 156 /** 157 * Get mapping from FuType to Latency value. 158 * If both [[latencyCertain]] and [[hasUncertainLatencyVal]] are false, get empty [[Map]] 159 * 160 * @return Map[ [[BigInt]], Latency] 161 */ 162 def fuLatencyMap: Map[FuType.OHType, Int] = { 163 if (latencyCertain) 164 if(needOg2) fuConfigs.map(x => (x.fuType, x.latency.latencyVal.get + 1)).toMap else fuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 165 else if (hasUncertainLatencyVal) 166 fuConfigs.map(x => (x.fuType, x.latency.uncertainLatencyVal)).toMap.filter(_._2.nonEmpty).map(x => (x._1, x._2.get)) 167 else 168 Map() 169 } 170 def wakeUpFuLatencyMap: Map[FuType.OHType, Int] = { 171 if (latencyCertain) 172 fuConfigs.filterNot(_.hasNoDataWB).map(x => (x.fuType, x.latency.latencyVal.get)).toMap 173 else if (hasUncertainLatencyVal) 174 fuConfigs.filterNot(_.hasNoDataWB).map(x => (x.fuType, x.latency.uncertainLatencyVal.get)).toMap 175 else 176 Map() 177 } 178 179 /** 180 * Get set of latency of function units. 181 * If both [[latencyCertain]] and [[hasUncertainLatencyVal]] are false, get empty [[Set]] 182 * 183 * @return Set[Latency] 184 */ 185 def fuLatancySet: Set[Int] = fuLatencyMap.values.toSet 186 187 def wakeUpFuLatancySet: Set[Int] = wakeUpFuLatencyMap.values.toSet 188 189 def latencyValMax: Int = fuLatancySet.fold(0)(_ max _) 190 191 def intFuLatencyMap: Map[FuType.OHType, Int] = { 192 if (intLatencyCertain) { 193 if (isVfExeUnit) { 194 // vf exe unit writing back to int regfile should delay 1 cycle 195 // vf exe unit need og2 --> delay 1 cycle 196 writeIntFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get + 2)).toMap 197 } else { 198 writeIntFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 199 } 200 } 201 else 202 Map() 203 } 204 205 def intLatencyValMax: Int = intFuLatencyMap.values.fold(0)(_ max _) 206 207 def fpFuLatencyMap: Map[FuType.OHType, Int] = { 208 if (fpLatencyCertain) 209 writeFpFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 210 else 211 Map() 212 } 213 214 def fpLatencyValMax: Int = fpFuLatencyMap.values.fold(0)(_ max _) 215 216 def vfFuLatencyMap: Map[FuType.OHType, Int] = { 217 if (vfLatencyCertain) 218 if(needOg2) writeVfFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get + 1)).toMap else writeVfFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 219 else 220 Map() 221 } 222 223 def vfLatencyValMax: Int = vfFuLatencyMap.values.fold(0)(_ max _) 224 225 def v0FuLatencyMap: Map[FuType.OHType, Int] = { 226 if (v0LatencyCertain) 227 if(needOg2) writeV0FuConfigs.map(x => (x.fuType, x.latency.latencyVal.get + 1)).toMap else writeV0FuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 228 else 229 Map() 230 } 231 232 def v0LatencyValMax: Int = v0FuLatencyMap.values.fold(0)(_ max _) 233 234 def vlFuLatencyMap: Map[FuType.OHType, Int] = { 235 if (vlLatencyCertain) 236 if(needOg2) writeVlFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get + 1)).toMap else writeVlFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 237 else 238 Map() 239 } 240 241 def vlLatencyValMax: Int = vlFuLatencyMap.values.fold(0)(_ max _) 242 243 /** 244 * Check if this exu has fixed latency 245 */ 246 def isFixedLatency: Boolean = { 247 if (latencyCertain) 248 return fuConfigs.map(x => x.latency.latencyVal.get == fuConfigs.head.latency.latencyVal.get).reduce(_ && _) 249 false 250 } 251 252 def hasCSR: Boolean = fuConfigs.map(_.isCsr).reduce(_ || _) 253 254 def hasFence: Boolean = fuConfigs.map(_.isFence).reduce(_ || _) 255 256 def hasBrhFu = fuConfigs.map(_.fuType == FuType.brh).reduce(_ || _) 257 258 def hasi2vFu = fuConfigs.map(_.fuType == FuType.i2v).reduce(_ || _) 259 260 def hasJmpFu = fuConfigs.map(_.fuType == FuType.jmp).reduce(_ || _) 261 262 def hasLoadFu = fuConfigs.map(_.name == "ldu").reduce(_ || _) 263 264 def hasVLoadFu = fuConfigs.map(_.fuType == FuType.vldu).reduce(_ || _) 265 266 def hasVStoreFu = fuConfigs.map(_.fuType == FuType.vstu).reduce(_ || _) 267 268 def hasVecLsFu = fuConfigs.map(x => FuType.FuTypeOrR(x.fuType, Seq(FuType.vldu, FuType.vstu))).reduce(_ || _) 269 270 def hasStoreAddrFu = fuConfigs.map(_.name == "sta").reduce(_ || _) 271 272 def hasStdFu = fuConfigs.map(_.name == "std").reduce(_ || _) 273 274 def hasMemAddrFu = hasLoadFu || hasStoreAddrFu || hasVLoadFu || hasHyldaFu || hasHystaFu || hasVLoadFu || hasVStoreFu 275 276 def hasHyldaFu = fuConfigs.map(_.name == "hylda").reduce(_ || _) 277 278 def hasHystaFu = fuConfigs.map(_.name == "hysta").reduce(_ || _) 279 280 def hasLoadExu = hasLoadFu || hasHyldaFu 281 282 def hasStoreAddrExu = hasStoreAddrFu || hasHystaFu 283 284 def hasVecFu = fuConfigs.map(x => FuConfig.VecArithFuConfigs.contains(x)).reduce(_ || _) 285 286 def CanCompress = !hasBrhFu || (hasBrhFu && hasi2vFu) 287 288 def getSrcDataType(srcIdx: Int): Set[DataConfig] = { 289 fuConfigs.map(_.getSrcDataType(srcIdx)).reduce(_ ++ _) 290 } 291 292 def immType: Set[UInt] = fuConfigs.map(x => x.immType).reduce(_ ++ _) 293 294 def getWBSource: SchedulerType = { 295 schdType 296 } 297 298 def hasCrossWb: Boolean = { 299 schdType match { 300 case IntScheduler() => writeFpRf || writeVecRf 301 case VfScheduler() => writeIntRf 302 case _ => false 303 } 304 } 305 306 def canAccept(fuType: UInt): Bool = { 307 Cat(fuConfigs.map(_.fuType.U === fuType)).orR 308 } 309 310 def hasUncertainLatency: Boolean = fuConfigs.map(_.latency.latencyVal.isEmpty).reduce(_ || _) 311 312 def bindBackendParam(param: BackendParams): Unit = { 313 backendParam = param 314 } 315 316 def updateIQWakeUpConfigs(cfgs: Seq[WakeUpConfig]) = { 317 this.iqWakeUpSourcePairs = cfgs.filter(_.source.name == this.name) 318 this.iqWakeUpSinkPairs = cfgs.filter(_.sink.name == this.name) 319 if (this.isIQWakeUpSource) { 320 require(!this.hasUncertainLatency || hasLoadFu || hasHyldaFu, s"${this.name} is a not-LDU IQ wake up source , but has UncertainLatency") 321 } 322 } 323 324 def updateExuIdx(idx: Int): Unit = { 325 this.exuIdx = idx 326 } 327 328 def isIQWakeUpSource = this.iqWakeUpSourcePairs.nonEmpty 329 330 def isIQWakeUpSink = this.iqWakeUpSinkPairs.nonEmpty 331 332 def getIntWBPort = { 333 wbPortConfigs.collectFirst { 334 case x: IntWB => x 335 } 336 } 337 338 def getFpWBPort = { 339 wbPortConfigs.collectFirst { 340 case x: FpWB => x 341 } 342 } 343 344 def getVfWBPort = { 345 wbPortConfigs.collectFirst { 346 case x: VfWB => x 347 } 348 } 349 350 def getV0WBPort = { 351 wbPortConfigs.collectFirst { 352 case x: V0WB => x 353 } 354 } 355 356 def getVlWBPort = { 357 wbPortConfigs.collectFirst { 358 case x: VlWB => x 359 } 360 } 361 362 /** 363 * Get the [[DataConfig]] that this exu need to read 364 */ 365 def pregRdDataCfgSet: Set[DataConfig] = { 366 this.rfrPortConfigs.flatten.map(_.getDataConfig).toSet 367 } 368 369 /** 370 * Get the [[DataConfig]] that this exu need to write 371 */ 372 def pregWbDataCfgSet: Set[DataConfig] = { 373 this.wbPortConfigs.map(_.dataCfg).toSet 374 } 375 376 def getRfReadDataCfgSet: Seq[Set[DataConfig]] = { 377 val fuSrcsCfgSet: Seq[Seq[Set[DataConfig]]] = fuConfigs.map(_.getRfReadDataCfgSet) 378 val alignedFuSrcsCfgSet: Seq[Seq[Set[DataConfig]]] = fuSrcsCfgSet.map(x => x ++ Seq.fill(numRegSrc - x.length)(Set[DataConfig]())) 379 380 val exuSrcsCfgSet = alignedFuSrcsCfgSet.reduce((x, y) => (x zip y).map { case (cfg1, cfg2) => cfg1 union cfg2 }) 381 382 exuSrcsCfgSet 383 } 384 385 /** 386 * Get the [[DataConfig]] mapped indices of source data of exu 387 * 388 * @example 389 * {{{ 390 * fuCfg.srcData = Seq(VecData(), VecData(), VecData(), V0Data(), VlData()) 391 * getRfReadSrcIdx(VecData()) = Seq(0, 1, 2) 392 * getRfReadSrcIdx(V0Data()) = Seq(3) 393 * getRfReadSrcIdx(VlData()) = Seq(4) 394 * }}} 395 * @return Map[DataConfig -> Seq[indices]] 396 */ 397 def getRfReadSrcIdx: Map[DataConfig, Seq[Int]] = { 398 val dataCfgs = DataConfig.RegSrcDataSet 399 val rfRdDataCfgSet = this.getRfReadDataCfgSet 400 dataCfgs.toSeq.map { cfg => 401 ( 402 cfg, 403 rfRdDataCfgSet.zipWithIndex.map { case (set, srcIdx) => 404 if (set.contains(cfg)) 405 Option(srcIdx) 406 else 407 None 408 }.filter(_.nonEmpty).map(_.get) 409 ) 410 }.toMap 411 } 412 413 def genExuModule(implicit p: Parameters): ExeUnit = { 414 new ExeUnit(this) 415 } 416 417 def genExuInputBundle(implicit p: Parameters): ExuInput = { 418 new ExuInput(this) 419 } 420 421 def genExuOutputBundle(implicit p: Parameters): ExuOutput = { 422 new ExuOutput(this) 423 } 424 425 def genExuBypassBundle(implicit p: Parameters): ExuBypassBundle = { 426 new ExuBypassBundle(this) 427 } 428} 429