1package xiangshan.backend.exu 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import xiangshan.backend.BackendParams 7import xiangshan.backend.Bundles.{ExuBypassBundle, ExuInput, ExuOutput} 8import xiangshan.backend.datapath.DataConfig.DataConfig 9import xiangshan.backend.datapath.RdConfig._ 10import xiangshan.backend.datapath.WbConfig._ 11import xiangshan.backend.datapath.{DataConfig, WakeUpConfig} 12import xiangshan.backend.fu.{FuConfig, FuType} 13import xiangshan.backend.issue.{IssueBlockParams, SchedulerType, IntScheduler, VfScheduler, MemScheduler} 14import scala.collection.mutable 15 16case class ExeUnitParams( 17 name : String, 18 fuConfigs : Seq[FuConfig], 19 wbPortConfigs : Seq[PregWB], 20 rfrPortConfigs: Seq[Seq[RdConfig]], 21 copyWakeupOut: Boolean = false, 22 copyDistance: Int = 1, 23 fakeUnit : Boolean = false, 24)( 25 implicit 26 val schdType: SchedulerType, 27) { 28 // calculated configs 29 var iqWakeUpSourcePairs: Seq[WakeUpConfig] = Seq() 30 var iqWakeUpSinkPairs: Seq[WakeUpConfig] = Seq() 31 var needLoadDependency: Boolean = false 32 // used in bypass to select data of exu output 33 var exuIdx: Int = -1 34 var backendParam: BackendParams = null 35 36 val numIntSrc: Int = fuConfigs.map(_.numIntSrc).max 37 val numFpSrc: Int = fuConfigs.map(_.numFpSrc).max 38 val numVecSrc: Int = fuConfigs.map(_.numVecSrc).max 39 val numVfSrc: Int = fuConfigs.map(_.numVfSrc).max 40 val numV0Src: Int = fuConfigs.map(_.numV0Src).max 41 val numVlSrc: Int = fuConfigs.map(_.numVlSrc).max 42 val numRegSrc: Int = fuConfigs.map(_.numRegSrc).max 43 val numSrc: Int = fuConfigs.map(_.numSrc).max 44 val destDataBitsMax: Int = fuConfigs.map(_.destDataBits).max 45 val srcDataBitsMax: Int = fuConfigs.map(x => x.srcDataBits.getOrElse(x.destDataBits)).max 46 val readIntRf: Boolean = numIntSrc > 0 47 val readFpRf: Boolean = numFpSrc > 0 48 val readVecRf: Boolean = numVecSrc > 0 49 val readVfRf: Boolean = numVfSrc > 0 50 val readVlRf: Boolean = numVlSrc > 0 51 val writeIntRf: Boolean = fuConfigs.map(_.writeIntRf).reduce(_ || _) 52 val writeFpRf: Boolean = fuConfigs.map(_.writeFpRf).reduce(_ || _) 53 val writeVecRf: Boolean = fuConfigs.map(_.writeVecRf).reduce(_ || _) 54 val writeV0Rf: Boolean = fuConfigs.map(_.writeV0Rf).reduce(_ || _) 55 val writeVlRf: Boolean = fuConfigs.map(_.writeVlRf).reduce(_ || _) 56 val needIntWen: Boolean = fuConfigs.map(_.needIntWen).reduce(_ || _) 57 val needFpWen: Boolean = fuConfigs.map(_.needFpWen).reduce(_ || _) 58 val needVecWen: Boolean = fuConfigs.map(_.needVecWen).reduce(_ || _) 59 val needV0Wen: Boolean = fuConfigs.map(_.needV0Wen).reduce(_ || _) 60 val needVlWen: Boolean = fuConfigs.map(_.needVlWen).reduce(_ || _) 61 val needOg2: Boolean = fuConfigs.map(_.needOg2).reduce(_ || _) 62 val writeVfRf: Boolean = writeVecRf 63 val writeFflags: Boolean = fuConfigs.map(_.writeFflags).reduce(_ || _) 64 val writeVxsat: Boolean = fuConfigs.map(_.writeVxsat).reduce(_ || _) 65 val hasNoDataWB: Boolean = fuConfigs.map(_.hasNoDataWB).reduce(_ && _) 66 val hasRedirect: Boolean = fuConfigs.map(_.hasRedirect).reduce(_ || _) 67 val hasPredecode: Boolean = fuConfigs.map(_.hasPredecode).reduce(_ || _) 68 val exceptionOut: Seq[Int] = fuConfigs.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted 69 val hasLoadError: Boolean = fuConfigs.map(_.hasLoadError).reduce(_ || _) 70 val flushPipe: Boolean = fuConfigs.map(_.flushPipe).reduce(_ || _) 71 val replayInst: Boolean = fuConfigs.map(_.replayInst).reduce(_ || _) 72 val trigger: Boolean = fuConfigs.map(_.trigger).reduce(_ || _) 73 val needExceptionGen: Boolean = exceptionOut.nonEmpty || flushPipe || replayInst || trigger 74 val needPc: Boolean = fuConfigs.map(_.needPc).reduce(_ || _) 75 val needTarget: Boolean = fuConfigs.map(_.needTargetPc).reduce(_ || _) 76 val needPdInfo: Boolean = fuConfigs.map(_.needPdInfo).reduce(_ || _) 77 val needSrcFrm: Boolean = fuConfigs.map(_.needSrcFrm).reduce(_ || _) 78 val needSrcVxrm: Boolean = fuConfigs.map(_.needSrcVxrm).reduce(_ || _) 79 val needFPUCtrl: Boolean = fuConfigs.map(_.needFPUCtrl).reduce(_ || _) 80 val needVPUCtrl: Boolean = fuConfigs.map(_.needVecCtrl).reduce(_ || _) 81 val writeVConfig: Boolean = fuConfigs.map(_.writeVlRf).reduce(_ || _) 82 val writeVType: Boolean = fuConfigs.map(_.writeVType).reduce(_ || _) 83 val needCriticalErrors: Boolean = fuConfigs.map(_.needCriticalErrors).reduce(_ || _) 84 val isHighestWBPriority: Boolean = wbPortConfigs.forall(_.priority == 0) 85 86 val isIntExeUnit: Boolean = schdType.isInstanceOf[IntScheduler] 87 val isVfExeUnit: Boolean = schdType.isInstanceOf[VfScheduler] 88 val isMemExeUnit: Boolean = schdType.isInstanceOf[MemScheduler] 89 90 def needReadRegCache: Boolean = isIntExeUnit || isMemExeUnit && readIntRf 91 def needWriteRegCache: Boolean = isIntExeUnit && isIQWakeUpSource || isMemExeUnit && isIQWakeUpSource && readIntRf 92 93 // exu writeback: 0 normalout; 1 intout; 2 fpout; 3 vecout 94 val wbNeedIntWen : Boolean = writeIntRf && !isMemExeUnit 95 val wbNeedFpWen : Boolean = writeFpRf && !isMemExeUnit 96 val wbNeedVecWen : Boolean = writeVecRf && !isMemExeUnit 97 val wbNeedV0Wen : Boolean = writeV0Rf && !isMemExeUnit 98 val wbNeedVlWen : Boolean = writeVlRf && !isMemExeUnit 99 val wbPathNum: Int = Seq(wbNeedIntWen, wbNeedFpWen, wbNeedVecWen, wbNeedV0Wen, wbNeedVlWen).count(_ == true) + 1 100 val wbNeeds = Seq( 101 ("int", wbNeedIntWen), 102 ("fp", wbNeedFpWen), 103 ("vec", wbNeedVecWen), 104 ("v0", wbNeedV0Wen), 105 ("vl", wbNeedVlWen) 106 ) 107 val wbIndexeds = wbNeeds.filter(_._2).zipWithIndex.map { 108 case ((label, _), index) => (label, index + 1) 109 }.toMap 110 val wbIntIndex: Int = wbIndexeds.getOrElse("int", 0) 111 val wbFpIndex : Int = wbIndexeds.getOrElse("fp", 0) 112 val wbVecIndex: Int = wbIndexeds.getOrElse("vec", 0) 113 val wbV0Index : Int = wbIndexeds.getOrElse("v0" , 0) 114 val wbVlIndex : Int = wbIndexeds.getOrElse("vl" , 0) 115 val wbIndex: Seq[Int] = Seq(wbIntIndex, wbFpIndex, wbVecIndex, wbV0Index, wbVlIndex) 116 117 118 def copyNum: Int = { 119 val setIQ = mutable.Set[IssueBlockParams]() 120 iqWakeUpSourcePairs.map(_.sink).foreach{ wakeupSink => 121 backendParam.allIssueParams.map{ issueParams => 122 if (issueParams.exuBlockParams.contains(wakeupSink.getExuParam(backendParam.allExuParams))) { 123 setIQ.add(issueParams) 124 } 125 } 126 } 127 println(s"[Backend] exuIdx ${exuIdx} numWakeupIQ ${setIQ.size}") 128 1 + setIQ.size / copyDistance 129 } 130 def rdPregIdxWidth: Int = { 131 this.pregRdDataCfgSet.map(dataCfg => backendParam.getPregParams(dataCfg).addrWidth).fold(0)(_ max _) 132 } 133 134 def wbPregIdxWidth: Int = { 135 this.pregWbDataCfgSet.map(dataCfg => backendParam.getPregParams(dataCfg).addrWidth).fold(0)(_ max _) 136 } 137 138 val writeIntFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeIntRf) 139 val writeFpFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeFpRf) 140 val writeVfFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeVecRf) 141 val writeV0FuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeV0Rf) 142 val writeVlFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeVlRf) 143 144 /** 145 * Check if this exu has certain latency 146 */ 147 def latencyCertain: Boolean = fuConfigs.map(x => x.latency.latencyVal.nonEmpty).reduce(_ && _) 148 def intLatencyCertain: Boolean = writeIntFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 149 def fpLatencyCertain: Boolean = writeFpFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 150 def vfLatencyCertain: Boolean = writeVfFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 151 def v0LatencyCertain: Boolean = writeV0FuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 152 def vlLatencyCertain: Boolean = writeVlFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 153 // only load use it 154 def hasUncertainLatencyVal: Boolean = fuConfigs.map(x => x.latency.uncertainLatencyVal.nonEmpty).reduce(_ || _) 155 156 /** 157 * Get mapping from FuType to Latency value. 158 * If both [[latencyCertain]] and [[hasUncertainLatencyVal]] are false, get empty [[Map]] 159 * 160 * @return Map[ [[BigInt]], Latency] 161 */ 162 def fuLatencyMap: Map[FuType.OHType, Int] = { 163 if (latencyCertain) 164 if(needOg2) fuConfigs.map(x => (x.fuType, x.latency.latencyVal.get + 1)).toMap else fuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 165 else if (hasUncertainLatencyVal) 166 fuConfigs.map(x => (x.fuType, x.latency.uncertainLatencyVal)).toMap.filter(_._2.nonEmpty).map(x => (x._1, x._2.get)) 167 else 168 Map() 169 } 170 def wakeUpFuLatencyMap: Map[FuType.OHType, Int] = { 171 if (latencyCertain) 172 fuConfigs.filterNot(_.hasNoDataWB).map(x => (x.fuType, x.latency.latencyVal.get)).toMap 173 else if (hasUncertainLatencyVal) 174 fuConfigs.filterNot(_.hasNoDataWB).map(x => (x.fuType, x.latency.uncertainLatencyVal.get)).toMap 175 else 176 Map() 177 } 178 179 /** 180 * Get set of latency of function units. 181 * If both [[latencyCertain]] and [[hasUncertainLatencyVal]] are false, get empty [[Set]] 182 * 183 * @return Set[Latency] 184 */ 185 def fuLatancySet: Set[Int] = fuLatencyMap.values.toSet 186 187 def wakeUpFuLatancySet: Set[Int] = wakeUpFuLatencyMap.values.toSet 188 189 def latencyValMax: Int = fuLatancySet.fold(0)(_ max _) 190 191 def intFuLatencyMap: Map[FuType.OHType, Int] = { 192 if (intLatencyCertain) { 193 if (isVfExeUnit) { 194 // vf exe unit writing back to int regfile should delay 1 cycle 195 // vf exe unit need og2 --> delay 1 cycle 196 writeIntFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get + 2)).toMap 197 } else { 198 writeIntFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 199 } 200 } 201 else 202 Map() 203 } 204 205 def intLatencyValMax: Int = intFuLatencyMap.values.fold(0)(_ max _) 206 207 def fpFuLatencyMap: Map[FuType.OHType, Int] = { 208 if (fpLatencyCertain) 209 if (needOg2) writeFpFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get + 1)).toMap else writeFpFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 210 else 211 Map() 212 } 213 214 def fpLatencyValMax: Int = fpFuLatencyMap.values.fold(0)(_ max _) 215 216 def vfFuLatencyMap: Map[FuType.OHType, Int] = { 217 if (vfLatencyCertain) 218 if(needOg2) writeVfFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get + 1)).toMap else writeVfFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 219 else 220 Map() 221 } 222 223 def vfLatencyValMax: Int = vfFuLatencyMap.values.fold(0)(_ max _) 224 225 def v0FuLatencyMap: Map[FuType.OHType, Int] = { 226 if (v0LatencyCertain) 227 if(needOg2) writeV0FuConfigs.map(x => (x.fuType, x.latency.latencyVal.get + 1)).toMap else writeV0FuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 228 else 229 Map() 230 } 231 232 def v0LatencyValMax: Int = v0FuLatencyMap.values.fold(0)(_ max _) 233 234 def vlFuLatencyMap: Map[FuType.OHType, Int] = { 235 if (vlLatencyCertain) 236 if(needOg2) writeVlFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get + 1)).toMap else writeVlFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 237 else 238 Map() 239 } 240 241 def vlLatencyValMax: Int = vlFuLatencyMap.values.fold(0)(_ max _) 242 243 /** 244 * Check if this exu has fixed latency 245 */ 246 def isFixedLatency: Boolean = { 247 if (latencyCertain) 248 return fuConfigs.map(x => x.latency.latencyVal.get == fuConfigs.head.latency.latencyVal.get).reduce(_ && _) 249 false 250 } 251 252 def hasCSR: Boolean = fuConfigs.map(_.isCsr).reduce(_ || _) 253 254 def hasFence: Boolean = fuConfigs.map(_.isFence).reduce(_ || _) 255 256 def hasBrhFu = fuConfigs.map(_.fuType == FuType.brh).reduce(_ || _) 257 258 def hasAluFu = fuConfigs.map(_.fuType == FuType.alu).reduce(_ || _) 259 260 def hasi2vFu = fuConfigs.map(_.fuType == FuType.i2v).reduce(_ || _) 261 262 def hasJmpFu = fuConfigs.map(_.fuType == FuType.jmp).reduce(_ || _) 263 264 def hasLoadFu = fuConfigs.map(_.name == "ldu").reduce(_ || _) 265 266 def hasVLoadFu = fuConfigs.map(_.fuType == FuType.vldu).reduce(_ || _) 267 268 def hasVStoreFu = fuConfigs.map(_.fuType == FuType.vstu).reduce(_ || _) 269 270 def hasVecLsFu = fuConfigs.map(x => FuType.FuTypeOrR(x.fuType, Seq(FuType.vldu, FuType.vstu))).reduce(_ || _) 271 272 def hasStoreAddrFu = fuConfigs.map(_.name == "sta").reduce(_ || _) 273 274 def hasStdFu = fuConfigs.map(_.name == "std").reduce(_ || _) 275 276 def hasMemAddrFu = hasLoadFu || hasStoreAddrFu || hasVLoadFu || hasHyldaFu || hasHystaFu || hasVLoadFu || hasVStoreFu 277 278 def hasHyldaFu = fuConfigs.map(_.name == "hylda").reduce(_ || _) 279 280 def hasHystaFu = fuConfigs.map(_.name == "hysta").reduce(_ || _) 281 282 def hasLoadExu = hasLoadFu || hasHyldaFu 283 284 def hasStoreAddrExu = hasStoreAddrFu || hasHystaFu 285 286 def hasVecFu = fuConfigs.map(x => FuConfig.VecArithFuConfigs.contains(x)).reduce(_ || _) 287 288 def CanCompress = !hasBrhFu || (hasBrhFu && hasi2vFu) 289 290 def getSrcDataType(srcIdx: Int): Set[DataConfig] = { 291 fuConfigs.map(_.getSrcDataType(srcIdx)).reduce(_ ++ _) 292 } 293 294 def immType: Set[UInt] = fuConfigs.map(x => x.immType).reduce(_ ++ _) 295 296 def getWBSource: SchedulerType = { 297 schdType 298 } 299 300 def hasCrossWb: Boolean = { 301 schdType match { 302 case IntScheduler() => writeFpRf || writeVecRf 303 case VfScheduler() => writeIntRf 304 case _ => false 305 } 306 } 307 308 def canAccept(fuType: UInt): Bool = { 309 Cat(fuConfigs.map(_.fuType.U === fuType)).orR 310 } 311 312 def hasUncertainLatency: Boolean = fuConfigs.map(_.latency.latencyVal.isEmpty).reduce(_ || _) 313 314 def bindBackendParam(param: BackendParams): Unit = { 315 backendParam = param 316 } 317 318 def updateIQWakeUpConfigs(cfgs: Seq[WakeUpConfig]) = { 319 this.iqWakeUpSourcePairs = cfgs.filter(_.source.name == this.name) 320 this.iqWakeUpSinkPairs = cfgs.filter(_.sink.name == this.name) 321 if (this.isIQWakeUpSource) { 322 require(!this.hasUncertainLatency || hasLoadFu || hasHyldaFu, s"${this.name} is a not-LDU IQ wake up source , but has UncertainLatency") 323 } 324 val loadWakeUpSourcePairs = cfgs.filter(x => x.source.getExuParam(backendParam.allExuParams).hasLoadFu || x.source.getExuParam(backendParam.allExuParams).hasHyldaFu) 325 val wakeUpByLoadNames = loadWakeUpSourcePairs.map(_.sink.name).toSet 326 val thisWakeUpByNames = iqWakeUpSinkPairs.map(_.source.name).toSet 327 this.needLoadDependency = !(wakeUpByLoadNames & thisWakeUpByNames).isEmpty 328 println(s"${this.name}: needLoadDependency is ${this.needLoadDependency}") 329 } 330 331 def updateExuIdx(idx: Int): Unit = { 332 this.exuIdx = idx 333 } 334 335 def isIQWakeUpSource = this.iqWakeUpSourcePairs.nonEmpty 336 337 def isIQWakeUpSink = this.iqWakeUpSinkPairs.nonEmpty 338 339 def numWakeupFromIQ = this.iqWakeUpSinkPairs.size 340 341 def getIntWBPort = { 342 wbPortConfigs.collectFirst { 343 case x: IntWB => x 344 } 345 } 346 347 def getFpWBPort = { 348 wbPortConfigs.collectFirst { 349 case x: FpWB => x 350 } 351 } 352 353 def getVfWBPort = { 354 wbPortConfigs.collectFirst { 355 case x: VfWB => x 356 } 357 } 358 359 def getV0WBPort = { 360 wbPortConfigs.collectFirst { 361 case x: V0WB => x 362 } 363 } 364 365 def getVlWBPort = { 366 wbPortConfigs.collectFirst { 367 case x: VlWB => x 368 } 369 } 370 371 /** 372 * Get the [[DataConfig]] that this exu need to read 373 */ 374 def pregRdDataCfgSet: Set[DataConfig] = { 375 this.rfrPortConfigs.flatten.map(_.getDataConfig).toSet 376 } 377 378 /** 379 * Get the [[DataConfig]] that this exu need to write 380 */ 381 def pregWbDataCfgSet: Set[DataConfig] = { 382 this.wbPortConfigs.map(_.dataCfg).toSet 383 } 384 385 def getRfReadDataCfgSet: Seq[Set[DataConfig]] = { 386 val fuSrcsCfgSet: Seq[Seq[Set[DataConfig]]] = fuConfigs.map(_.getRfReadDataCfgSet) 387 val alignedFuSrcsCfgSet: Seq[Seq[Set[DataConfig]]] = fuSrcsCfgSet.map(x => x ++ Seq.fill(numRegSrc - x.length)(Set[DataConfig]())) 388 389 val exuSrcsCfgSet = alignedFuSrcsCfgSet.reduce((x, y) => (x zip y).map { case (cfg1, cfg2) => cfg1 union cfg2 }) 390 391 exuSrcsCfgSet 392 } 393 394 /** 395 * Get the [[DataConfig]] mapped indices of source data of exu 396 * 397 * @example 398 * {{{ 399 * fuCfg.srcData = Seq(VecData(), VecData(), VecData(), V0Data(), VlData()) 400 * getRfReadSrcIdx(VecData()) = Seq(0, 1, 2) 401 * getRfReadSrcIdx(V0Data()) = Seq(3) 402 * getRfReadSrcIdx(VlData()) = Seq(4) 403 * }}} 404 * @return Map[DataConfig -> Seq[indices]] 405 */ 406 def getRfReadSrcIdx: Map[DataConfig, Seq[Int]] = { 407 val dataCfgs = DataConfig.RegSrcDataSet 408 val rfRdDataCfgSet = this.getRfReadDataCfgSet 409 dataCfgs.toSeq.map { cfg => 410 ( 411 cfg, 412 rfRdDataCfgSet.zipWithIndex.map { case (set, srcIdx) => 413 if (set.contains(cfg)) 414 Option(srcIdx) 415 else 416 None 417 }.filter(_.nonEmpty).map(_.get) 418 ) 419 }.toMap 420 } 421 422 def genExuModule(implicit p: Parameters): ExeUnit = { 423 new ExeUnit(this) 424 } 425 426 def genExuInputBundle(implicit p: Parameters): ExuInput = { 427 new ExuInput(this) 428 } 429 430 def genExuOutputBundle(implicit p: Parameters): ExuOutput = { 431 new ExuOutput(this) 432 } 433 434 def genExuBypassBundle(implicit p: Parameters): ExuBypassBundle = { 435 new ExuBypassBundle(this) 436 } 437} 438