1package xiangshan.backend.exu 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import xiangshan.backend.BackendParams 7import xiangshan.backend.Bundles.{ExuBypassBundle, ExuInput, ExuOutput} 8import xiangshan.backend.datapath.DataConfig.DataConfig 9import xiangshan.backend.datapath.RdConfig._ 10import xiangshan.backend.datapath.WbConfig._ 11import xiangshan.backend.datapath.{DataConfig, WakeUpConfig} 12import xiangshan.backend.fu.{FuConfig, FuType} 13import xiangshan.backend.issue.{IssueBlockParams, SchedulerType, IntScheduler, VfScheduler, MemScheduler} 14import scala.collection.mutable 15 16case class ExeUnitParams( 17 name : String, 18 fuConfigs : Seq[FuConfig], 19 wbPortConfigs : Seq[PregWB], 20 rfrPortConfigs: Seq[Seq[RdConfig]], 21 copyWakeupOut: Boolean = false, 22 copyDistance: Int = 1, 23 fakeUnit : Boolean = false, 24)( 25 implicit 26 val schdType: SchedulerType, 27) { 28 // calculated configs 29 var iqWakeUpSourcePairs: Seq[WakeUpConfig] = Seq() 30 var iqWakeUpSinkPairs: Seq[WakeUpConfig] = Seq() 31 // used in bypass to select data of exu output 32 var exuIdx: Int = -1 33 var backendParam: BackendParams = null 34 35 val numIntSrc: Int = fuConfigs.map(_.numIntSrc).max 36 val numFpSrc: Int = fuConfigs.map(_.numFpSrc).max 37 val numVecSrc: Int = fuConfigs.map(_.numVecSrc).max 38 val numVfSrc: Int = fuConfigs.map(_.numVfSrc).max 39 val numV0Src: Int = fuConfigs.map(_.numV0Src).max 40 val numVlSrc: Int = fuConfigs.map(_.numVlSrc).max 41 val numRegSrc: Int = fuConfigs.map(_.numRegSrc).max 42 val numSrc: Int = fuConfigs.map(_.numSrc).max 43 val destDataBitsMax: Int = fuConfigs.map(_.destDataBits).max 44 val srcDataBitsMax: Int = fuConfigs.map(x => x.srcDataBits.getOrElse(x.destDataBits)).max 45 val readIntRf: Boolean = numIntSrc > 0 46 val readFpRf: Boolean = numFpSrc > 0 47 val readVecRf: Boolean = numVecSrc > 0 48 val readVfRf: Boolean = numVfSrc > 0 49 val writeIntRf: Boolean = fuConfigs.map(_.writeIntRf).reduce(_ || _) 50 val writeFpRf: Boolean = fuConfigs.map(_.writeFpRf).reduce(_ || _) 51 val writeVecRf: Boolean = fuConfigs.map(_.writeVecRf).reduce(_ || _) 52 val writeV0Rf: Boolean = fuConfigs.map(_.writeV0Rf).reduce(_ || _) 53 val writeVlRf: Boolean = fuConfigs.map(_.writeVlRf).reduce(_ || _) 54 val needIntWen: Boolean = fuConfigs.map(_.needIntWen).reduce(_ || _) 55 val needFpWen: Boolean = fuConfigs.map(_.needFpWen).reduce(_ || _) 56 val needVecWen: Boolean = fuConfigs.map(_.needVecWen).reduce(_ || _) 57 val needV0Wen: Boolean = fuConfigs.map(_.needV0Wen).reduce(_ || _) 58 val needVlWen: Boolean = fuConfigs.map(_.needVlWen).reduce(_ || _) 59 val needOg2: Boolean = fuConfigs.map(_.needOg2).reduce(_ || _) 60 val writeVfRf: Boolean = writeVecRf 61 val writeFflags: Boolean = fuConfigs.map(_.writeFflags).reduce(_ || _) 62 val writeVxsat: Boolean = fuConfigs.map(_.writeVxsat).reduce(_ || _) 63 val hasNoDataWB: Boolean = fuConfigs.map(_.hasNoDataWB).reduce(_ && _) 64 val hasRedirect: Boolean = fuConfigs.map(_.hasRedirect).reduce(_ || _) 65 val hasPredecode: Boolean = fuConfigs.map(_.hasPredecode).reduce(_ || _) 66 val exceptionOut: Seq[Int] = fuConfigs.map(_.exceptionOut).reduce(_ ++ _).distinct.sorted 67 val hasLoadError: Boolean = fuConfigs.map(_.hasLoadError).reduce(_ || _) 68 val flushPipe: Boolean = fuConfigs.map(_.flushPipe).reduce(_ || _) 69 val replayInst: Boolean = fuConfigs.map(_.replayInst).reduce(_ || _) 70 val trigger: Boolean = fuConfigs.map(_.trigger).reduce(_ || _) 71 val needExceptionGen: Boolean = exceptionOut.nonEmpty || flushPipe || replayInst || trigger 72 val needPc: Boolean = fuConfigs.map(_.needPc).reduce(_ || _) 73 val needTarget: Boolean = fuConfigs.map(_.needTargetPc).reduce(_ || _) 74 val needPdInfo: Boolean = fuConfigs.map(_.needPdInfo).reduce(_ || _) 75 val needSrcFrm: Boolean = fuConfigs.map(_.needSrcFrm).reduce(_ || _) 76 val needSrcVxrm: Boolean = fuConfigs.map(_.needSrcVxrm).reduce(_ || _) 77 val needFPUCtrl: Boolean = fuConfigs.map(_.needFPUCtrl).reduce(_ || _) 78 val needVPUCtrl: Boolean = fuConfigs.map(_.needVecCtrl).reduce(_ || _) 79 val writeVConfig: Boolean = fuConfigs.map(_.writeVlRf).reduce(_ || _) 80 val writeVType: Boolean = fuConfigs.map(_.writeVType).reduce(_ || _) 81 val isHighestWBPriority: Boolean = wbPortConfigs.forall(_.priority == 0) 82 83 val isIntExeUnit: Boolean = schdType.isInstanceOf[IntScheduler] 84 val isVfExeUnit: Boolean = schdType.isInstanceOf[VfScheduler] 85 val isMemExeUnit: Boolean = schdType.isInstanceOf[MemScheduler] 86 87 val needReadRegCache: Boolean = isIntExeUnit || isMemExeUnit && readIntRf 88 89 // exu writeback: 0 normalout; 1 intout; 2 fpout; 3 vecout 90 val wbNeedIntWen : Boolean = writeIntRf && !isMemExeUnit 91 val wbNeedFpWen : Boolean = writeFpRf && !isMemExeUnit 92 val wbNeedVecWen : Boolean = writeVecRf && !isMemExeUnit 93 val wbNeedV0Wen : Boolean = writeV0Rf && !isMemExeUnit 94 val wbNeedVlWen : Boolean = writeVlRf && !isMemExeUnit 95 val wbPathNum: Int = Seq(wbNeedIntWen, wbNeedFpWen, wbNeedVecWen, wbNeedV0Wen, wbNeedVlWen).count(_ == true) + 1 96 val wbNeeds = Seq( 97 ("int", wbNeedIntWen), 98 ("fp", wbNeedFpWen), 99 ("vec", wbNeedVecWen), 100 ("v0", wbNeedV0Wen), 101 ("vl", wbNeedVlWen) 102 ) 103 val wbIndexeds = wbNeeds.filter(_._2).zipWithIndex.map { 104 case ((label, _), index) => (label, index + 1) 105 }.toMap 106 val wbIntIndex: Int = wbIndexeds.getOrElse("int", 0) 107 val wbFpIndex : Int = wbIndexeds.getOrElse("fp", 0) 108 val wbVecIndex: Int = wbIndexeds.getOrElse("vec", 0) 109 val wbV0Index : Int = wbIndexeds.getOrElse("v0" , 0) 110 val wbVlIndex : Int = wbIndexeds.getOrElse("vl" , 0) 111 val wbIndex: Seq[Int] = Seq(wbIntIndex, wbFpIndex, wbVecIndex, wbV0Index, wbVlIndex) 112 113 114 115 require(needPc && needTarget || !needPc && !needTarget, "The ExeUnit must need both PC and Target PC") 116 117 def copyNum: Int = { 118 val setIQ = mutable.Set[IssueBlockParams]() 119 iqWakeUpSourcePairs.map(_.sink).foreach{ wakeupSink => 120 backendParam.allIssueParams.map{ issueParams => 121 if (issueParams.exuBlockParams.contains(wakeupSink.getExuParam(backendParam.allExuParams))) { 122 setIQ.add(issueParams) 123 } 124 } 125 } 126 println(s"[Backend] exuIdx ${exuIdx} numWakeupIQ ${setIQ.size}") 127 1 + setIQ.size / copyDistance 128 } 129 def rdPregIdxWidth: Int = { 130 this.pregRdDataCfgSet.map(dataCfg => backendParam.getPregParams(dataCfg).addrWidth).fold(0)(_ max _) 131 } 132 133 def wbPregIdxWidth: Int = { 134 this.pregWbDataCfgSet.map(dataCfg => backendParam.getPregParams(dataCfg).addrWidth).fold(0)(_ max _) 135 } 136 137 val writeIntFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeIntRf) 138 val writeFpFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeFpRf) 139 val writeVfFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeVecRf) 140 val writeV0FuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeV0Rf) 141 val writeVlFuConfigs: Seq[FuConfig] = fuConfigs.filter(x => x.writeVlRf) 142 143 /** 144 * Check if this exu has certain latency 145 */ 146 def latencyCertain: Boolean = fuConfigs.map(x => x.latency.latencyVal.nonEmpty).reduce(_ && _) 147 def intLatencyCertain: Boolean = writeIntFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 148 def fpLatencyCertain: Boolean = writeFpFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 149 def vfLatencyCertain: Boolean = writeVfFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 150 def v0LatencyCertain: Boolean = writeV0FuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 151 def vlLatencyCertain: Boolean = writeVlFuConfigs.forall(x => x.latency.latencyVal.nonEmpty) 152 // only load use it 153 def hasUncertainLatencyVal: Boolean = fuConfigs.map(x => x.latency.uncertainLatencyVal.nonEmpty).reduce(_ || _) 154 155 /** 156 * Get mapping from FuType to Latency value. 157 * If both [[latencyCertain]] and [[hasUncertainLatencyVal]] are false, get empty [[Map]] 158 * 159 * @return Map[ [[BigInt]], Latency] 160 */ 161 def fuLatencyMap: Map[FuType.OHType, Int] = { 162 if (latencyCertain) 163 if(needOg2) fuConfigs.map(x => (x.fuType, x.latency.latencyVal.get + 1)).toMap else fuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 164 else if (hasUncertainLatencyVal) 165 fuConfigs.map(x => (x.fuType, x.latency.uncertainLatencyVal)).toMap.filter(_._2.nonEmpty).map(x => (x._1, x._2.get)) 166 else 167 Map() 168 } 169 def wakeUpFuLatencyMap: Map[FuType.OHType, Int] = { 170 if (latencyCertain) 171 fuConfigs.filterNot(_.hasNoDataWB).map(x => (x.fuType, x.latency.latencyVal.get)).toMap 172 else if (hasUncertainLatencyVal) 173 fuConfigs.filterNot(_.hasNoDataWB).map(x => (x.fuType, x.latency.uncertainLatencyVal.get)).toMap 174 else 175 Map() 176 } 177 178 /** 179 * Get set of latency of function units. 180 * If both [[latencyCertain]] and [[hasUncertainLatencyVal]] are false, get empty [[Set]] 181 * 182 * @return Set[Latency] 183 */ 184 def fuLatancySet: Set[Int] = fuLatencyMap.values.toSet 185 186 def wakeUpFuLatancySet: Set[Int] = wakeUpFuLatencyMap.values.toSet 187 188 def latencyValMax: Int = fuLatancySet.fold(0)(_ max _) 189 190 def intFuLatencyMap: Map[FuType.OHType, Int] = { 191 if (intLatencyCertain) { 192 if (isVfExeUnit) { 193 // vf exe unit writing back to int regfile should delay 1 cycle 194 // vf exe unit need og2 --> delay 1 cycle 195 writeIntFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get + 2)).toMap 196 } else { 197 writeIntFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 198 } 199 } 200 else 201 Map() 202 } 203 204 def intLatencyValMax: Int = intFuLatencyMap.values.fold(0)(_ max _) 205 206 def fpFuLatencyMap: Map[FuType.OHType, Int] = { 207 if (fpLatencyCertain) 208 writeFpFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 209 else 210 Map() 211 } 212 213 def fpLatencyValMax: Int = fpFuLatencyMap.values.fold(0)(_ max _) 214 215 def vfFuLatencyMap: Map[FuType.OHType, Int] = { 216 if (vfLatencyCertain) 217 if(needOg2) writeVfFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get + 1)).toMap else writeVfFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 218 else 219 Map() 220 } 221 222 def vfLatencyValMax: Int = vfFuLatencyMap.values.fold(0)(_ max _) 223 224 def v0FuLatencyMap: Map[FuType.OHType, Int] = { 225 if (v0LatencyCertain) 226 if(needOg2) writeV0FuConfigs.map(x => (x.fuType, x.latency.latencyVal.get + 1)).toMap else writeV0FuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 227 else 228 Map() 229 } 230 231 def v0LatencyValMax: Int = v0FuLatencyMap.values.fold(0)(_ max _) 232 233 def vlFuLatencyMap: Map[FuType.OHType, Int] = { 234 if (vlLatencyCertain) 235 if(needOg2) writeVlFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get + 1)).toMap else writeVlFuConfigs.map(x => (x.fuType, x.latency.latencyVal.get)).toMap 236 else 237 Map() 238 } 239 240 def vlLatencyValMax: Int = vlFuLatencyMap.values.fold(0)(_ max _) 241 242 /** 243 * Check if this exu has fixed latency 244 */ 245 def isFixedLatency: Boolean = { 246 if (latencyCertain) 247 return fuConfigs.map(x => x.latency.latencyVal.get == fuConfigs.head.latency.latencyVal.get).reduce(_ && _) 248 false 249 } 250 251 def hasCSR: Boolean = fuConfigs.map(_.isCsr).reduce(_ || _) 252 253 def hasFence: Boolean = fuConfigs.map(_.isFence).reduce(_ || _) 254 255 def hasBrhFu = fuConfigs.map(_.fuType == FuType.brh).reduce(_ || _) 256 257 def hasi2vFu = fuConfigs.map(_.fuType == FuType.i2v).reduce(_ || _) 258 259 def hasJmpFu = fuConfigs.map(_.fuType == FuType.jmp).reduce(_ || _) 260 261 def hasLoadFu = fuConfigs.map(_.name == "ldu").reduce(_ || _) 262 263 def hasVLoadFu = fuConfigs.map(_.fuType == FuType.vldu).reduce(_ || _) 264 265 def hasVStoreFu = fuConfigs.map(_.fuType == FuType.vstu).reduce(_ || _) 266 267 def hasVecLsFu = fuConfigs.map(x => FuType.FuTypeOrR(x.fuType, Seq(FuType.vldu, FuType.vstu))).reduce(_ || _) 268 269 def hasStoreAddrFu = fuConfigs.map(_.name == "sta").reduce(_ || _) 270 271 def hasStdFu = fuConfigs.map(_.name == "std").reduce(_ || _) 272 273 def hasMemAddrFu = hasLoadFu || hasStoreAddrFu || hasVLoadFu || hasHyldaFu || hasHystaFu || hasVLoadFu || hasVStoreFu 274 275 def hasHyldaFu = fuConfigs.map(_.name == "hylda").reduce(_ || _) 276 277 def hasHystaFu = fuConfigs.map(_.name == "hysta").reduce(_ || _) 278 279 def hasLoadExu = hasLoadFu || hasHyldaFu 280 281 def hasStoreAddrExu = hasStoreAddrFu || hasHystaFu 282 283 def hasVecFu = fuConfigs.map(x => FuConfig.VecArithFuConfigs.contains(x)).reduce(_ || _) 284 285 def CanCompress = !hasBrhFu || (hasBrhFu && hasi2vFu) 286 287 def getSrcDataType(srcIdx: Int): Set[DataConfig] = { 288 fuConfigs.map(_.getSrcDataType(srcIdx)).reduce(_ ++ _) 289 } 290 291 def immType: Set[UInt] = fuConfigs.map(x => x.immType).reduce(_ ++ _) 292 293 def getWBSource: SchedulerType = { 294 schdType 295 } 296 297 def hasCrossWb: Boolean = { 298 schdType match { 299 case IntScheduler() => writeFpRf || writeVecRf 300 case VfScheduler() => writeIntRf 301 case _ => false 302 } 303 } 304 305 def canAccept(fuType: UInt): Bool = { 306 Cat(fuConfigs.map(_.fuType.U === fuType)).orR 307 } 308 309 def hasUncertainLatency: Boolean = fuConfigs.map(_.latency.latencyVal.isEmpty).reduce(_ || _) 310 311 def bindBackendParam(param: BackendParams): Unit = { 312 backendParam = param 313 } 314 315 def updateIQWakeUpConfigs(cfgs: Seq[WakeUpConfig]) = { 316 this.iqWakeUpSourcePairs = cfgs.filter(_.source.name == this.name) 317 this.iqWakeUpSinkPairs = cfgs.filter(_.sink.name == this.name) 318 if (this.isIQWakeUpSource) { 319 require(!this.hasUncertainLatency || hasLoadFu || hasHyldaFu, s"${this.name} is a not-LDU IQ wake up source , but has UncertainLatency") 320 } 321 } 322 323 def updateExuIdx(idx: Int): Unit = { 324 this.exuIdx = idx 325 } 326 327 def isIQWakeUpSource = this.iqWakeUpSourcePairs.nonEmpty 328 329 def isIQWakeUpSink = this.iqWakeUpSinkPairs.nonEmpty 330 331 def getIntWBPort = { 332 wbPortConfigs.collectFirst { 333 case x: IntWB => x 334 } 335 } 336 337 def getFpWBPort = { 338 wbPortConfigs.collectFirst { 339 case x: FpWB => x 340 } 341 } 342 343 def getVfWBPort = { 344 wbPortConfigs.collectFirst { 345 case x: VfWB => x 346 } 347 } 348 349 def getV0WBPort = { 350 wbPortConfigs.collectFirst { 351 case x: V0WB => x 352 } 353 } 354 355 def getVlWBPort = { 356 wbPortConfigs.collectFirst { 357 case x: VlWB => x 358 } 359 } 360 361 /** 362 * Get the [[DataConfig]] that this exu need to read 363 */ 364 def pregRdDataCfgSet: Set[DataConfig] = { 365 this.rfrPortConfigs.flatten.map(_.getDataConfig).toSet 366 } 367 368 /** 369 * Get the [[DataConfig]] that this exu need to write 370 */ 371 def pregWbDataCfgSet: Set[DataConfig] = { 372 this.wbPortConfigs.map(_.dataCfg).toSet 373 } 374 375 def getRfReadDataCfgSet: Seq[Set[DataConfig]] = { 376 val fuSrcsCfgSet: Seq[Seq[Set[DataConfig]]] = fuConfigs.map(_.getRfReadDataCfgSet) 377 val alignedFuSrcsCfgSet: Seq[Seq[Set[DataConfig]]] = fuSrcsCfgSet.map(x => x ++ Seq.fill(numRegSrc - x.length)(Set[DataConfig]())) 378 379 val exuSrcsCfgSet = alignedFuSrcsCfgSet.reduce((x, y) => (x zip y).map { case (cfg1, cfg2) => cfg1 union cfg2 }) 380 381 exuSrcsCfgSet 382 } 383 384 /** 385 * Get the [[DataConfig]] mapped indices of source data of exu 386 * 387 * @example 388 * {{{ 389 * fuCfg.srcData = Seq(VecData(), VecData(), VecData(), V0Data(), VlData()) 390 * getRfReadSrcIdx(VecData()) = Seq(0, 1, 2) 391 * getRfReadSrcIdx(V0Data()) = Seq(3) 392 * getRfReadSrcIdx(VlData()) = Seq(4) 393 * }}} 394 * @return Map[DataConfig -> Seq[indices]] 395 */ 396 def getRfReadSrcIdx: Map[DataConfig, Seq[Int]] = { 397 val dataCfgs = DataConfig.RegSrcDataSet 398 val rfRdDataCfgSet = this.getRfReadDataCfgSet 399 dataCfgs.toSeq.map { cfg => 400 ( 401 cfg, 402 rfRdDataCfgSet.zipWithIndex.map { case (set, srcIdx) => 403 if (set.contains(cfg)) 404 Option(srcIdx) 405 else 406 None 407 }.filter(_.nonEmpty).map(_.get) 408 ) 409 }.toMap 410 } 411 412 def genExuModule(implicit p: Parameters): ExeUnit = { 413 new ExeUnit(this) 414 } 415 416 def genExuInputBundle(implicit p: Parameters): ExuInput = { 417 new ExuInput(this) 418 } 419 420 def genExuOutputBundle(implicit p: Parameters): ExuOutput = { 421 new ExuOutput(this) 422 } 423 424 def genExuBypassBundle(implicit p: Parameters): ExuBypassBundle = { 425 new ExuBypassBundle(this) 426 } 427} 428