1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* 4* XiangShan is licensed under Mulan PSL v2. 5* You can use this software according to the terms and conditions of the Mulan PSL v2. 6* You may obtain a copy of Mulan PSL v2 at: 7* http://license.coscl.org.cn/MulanPSL2 8* 9* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 10* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 11* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 12* 13* See the Mulan PSL v2 for more details. 14***************************************************************************************/ 15 16package xiangshan.backend.fu 17 18import chipsalliance.rocketchip.config.Parameters 19import chisel3._ 20import chisel3.util._ 21import xiangshan._ 22import utils._ 23 24abstract class AbstractDivider(len: Int)(implicit p: Parameters) extends FunctionUnit(len){ 25 val ctrl = IO(Input(new MulDivCtrl)) 26 val sign = ctrl.sign 27} 28 29class Radix2Divider(len: Int)(implicit p: Parameters) extends AbstractDivider(len) { 30 31 def abs(a: UInt, sign: Bool): (Bool, UInt) = { 32 val s = a(len - 1) && sign 33 (s, Mux(s, -a, a)) 34 } 35 36 val s_idle :: s_log2 :: s_shift :: s_compute :: s_finish :: Nil = Enum(5) 37 val state = RegInit(s_idle) 38 val newReq = (state === s_idle) && io.in.fire() 39 40 val (a, b) = (io.in.bits.src(0), io.in.bits.src(1)) 41 val divBy0 = b === 0.U(len.W) 42 val divBy0Reg = RegEnable(divBy0, newReq) 43 44 val shiftReg = Reg(UInt((1 + len * 2).W)) 45 val hi = shiftReg(len * 2, len) 46 val lo = shiftReg(len - 1, 0) 47 48 val uop = io.in.bits.uop 49 50 val (aSign, aVal) = abs(a, sign) 51 val (bSign, bVal) = abs(b, sign) 52 val aSignReg = RegEnable(aSign, newReq) 53 val qSignReg = RegEnable((aSign ^ bSign) && !divBy0, newReq) 54 val bReg = RegEnable(bVal, newReq) 55 val aValx2Reg = RegEnable(Cat(aVal, "b0".U), newReq) 56 val ctrlReg = RegEnable(ctrl, newReq) 57 val uopReg = RegEnable(uop, newReq) 58 59 val cnt = Counter(len) 60 when (newReq && !io.in.bits.uop.roqIdx.needFlush(io.redirectIn, io.flushIn)) { 61 state := s_log2 62 } .elsewhen (state === s_log2) { 63 // `canSkipShift` is calculated as following: 64 // bEffectiveBit = Log2(bVal, XLEN) + 1.U 65 // aLeadingZero = 64.U - aEffectiveBit = 64.U - (Log2(aVal, XLEN) + 1.U) 66 // canSkipShift = aLeadingZero + bEffectiveBit 67 // = 64.U - (Log2(aVal, XLEN) + 1.U) + Log2(bVal, XLEN) + 1.U 68 // = 64.U + Log2(bVal, XLEN) - Log2(aVal, XLEN) 69 // = (64.U | Log2(bVal, XLEN)) - Log2(aVal, XLEN) // since Log2(bVal, XLEN) < 64.U 70 val canSkipShift = (64.U | Log2(bReg)) - Log2(aValx2Reg) 71 // When divide by 0, the quotient should be all 1's. 72 // Therefore we can not shift in 0s here. 73 // We do not skip any shift to avoid this. 74 cnt.value := Mux(divBy0Reg, 0.U, Mux(canSkipShift >= (len-1).U, (len-1).U, canSkipShift)) 75 state := s_shift 76 } .elsewhen (state === s_shift) { 77 shiftReg := aValx2Reg << cnt.value 78 state := s_compute 79 } .elsewhen (state === s_compute) { 80 val enough = hi.asUInt >= bReg.asUInt 81 shiftReg := Cat(Mux(enough, hi - bReg, hi)(len - 1, 0), lo, enough) 82 cnt.inc() 83 when (cnt.value === (len-1).U) { state := s_finish } 84 } .elsewhen (state === s_finish) { 85 when(io.out.ready){ 86 state := s_idle 87 } 88 } 89 90 val kill = state=/=s_idle && uopReg.roqIdx.needFlush(io.redirectIn, io.flushIn) 91 when(kill){ 92 state := s_idle 93 } 94 95 val r = hi(len, 1) 96 val resQ = Mux(qSignReg, -lo, lo) 97 val resR = Mux(aSignReg, -r, r) 98 99 val xlen = io.out.bits.data.getWidth 100 val res = Mux(ctrlReg.isHi, resR, resQ) 101 io.out.bits.data := Mux(ctrlReg.isW, SignExt(res(31,0),xlen), res) 102 io.out.bits.uop := uopReg 103 104 io.out.valid := state === s_finish 105 io.in.ready := state === s_idle 106} 107