xref: /XiangShan/src/main/scala/system/SoC.scala (revision c6d439803a044ea209139672b25e35fe8d7f4aa0) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3*
4* XiangShan is licensed under Mulan PSL v2.
5* You can use this software according to the terms and conditions of the Mulan PSL v2.
6* You may obtain a copy of Mulan PSL v2 at:
7*          http://license.coscl.org.cn/MulanPSL2
8*
9* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
10* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
11* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
12*
13* See the Mulan PSL v2 for more details.
14***************************************************************************************/
15
16package system
17
18import chipsalliance.rocketchip.config.{Field, Parameters}
19import chisel3._
20import chisel3.util._
21import xiangshan.{DebugOptionsKey, HasXSParameter, XSBundle, XSCore, XSCoreParameters}
22import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, BusErrors, L1BusErrors}
23
24case object SoCParamsKey extends Field[SoCParameters]
25
26case class SoCParameters
27(
28  cores: List[XSCoreParameters],
29  EnableILA: Boolean = false,
30  extIntrs: Int = 150,
31  useFakeL3Cache: Boolean = false,
32  L3Size: Int = 4 * 1024 * 1024 // 4MB
33){
34  val PAddrBits = cores.map(_.PAddrBits).reduce((x, y) => if(x > y) x else y)
35  // L3 configurations
36  val L3InnerBusWidth = 256
37  val L3BlockSize = 64
38  val L3NBanks = 4
39  val L3NWays = 8
40
41  // on chip network configurations
42  val L3OuterBusWidth = 256
43
44}
45
46trait HasSoCParameter {
47  implicit val p: Parameters
48
49  val soc = p(SoCParamsKey)
50  val debugOpts = p(DebugOptionsKey)
51  val NumCores = soc.cores.size
52  val EnableILA = soc.EnableILA
53
54  // L3 configurations
55  val useFakeL3Cache = soc.useFakeL3Cache
56  val L3InnerBusWidth = soc.L3InnerBusWidth
57  val L3Size = soc.L3Size
58  val L3BlockSize = soc.L3BlockSize
59  val L3NBanks = soc.L3NBanks
60  val L3NWays = soc.L3NWays
61  val L3NSets = L3Size / L3BlockSize / L3NBanks / L3NWays
62
63  // on chip network configurations
64  val L3OuterBusWidth = soc.L3OuterBusWidth
65
66  val NrExtIntr = soc.extIntrs
67}
68
69class ILABundle extends Bundle {}
70
71
72class L1CacheErrorInfo(implicit val p: Parameters) extends Bundle with HasSoCParameter {
73  val paddr = Valid(UInt(soc.PAddrBits.W))
74  // for now, we only detect ecc
75  val ecc_error = Valid(Bool())
76}
77
78class XSL1BusErrors(val nCores: Int)(implicit val p: Parameters) extends BusErrors {
79  val icache = Vec(nCores, new L1CacheErrorInfo)
80  val l1plus = Vec(nCores, new L1CacheErrorInfo)
81  val dcache = Vec(nCores, new L1CacheErrorInfo)
82
83  override def toErrorList: List[Option[(ValidIO[UInt], String, String)]] =
84    List.tabulate(nCores){i =>
85      List(
86        Some(icache(i).paddr, s"IBUS_$i", s"Icache_$i bus error"),
87        Some(icache(i).ecc_error, s"I_ECC_$i", s"Icache_$i ecc error"),
88        Some(l1plus(i).paddr, s"L1PLUS_$i", s"L1PLUS_$i bus error"),
89        Some(l1plus(i).ecc_error, s"L1PLUS_ECC_$i", s"L1PLUS_$i ecc error"),
90        Some(dcache(i).paddr, s"DBUS_$i", s"Dcache_$i bus error"),
91        Some(dcache(i).ecc_error, s"D_ECC_$i", s"Dcache_$i ecc error")
92      )
93    }.flatten
94}
95