1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.backend.decode 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.rocket.Instructions 23import freechips.rocketchip.util.uintToBitPat 24import utils._ 25import utility._ 26import xiangshan.ExceptionNO.illegalInstr 27import xiangshan._ 28import xiangshan.backend.fu.fpu.FPU 29import xiangshan.backend.fu.FuType 30import freechips.rocketchip.rocket.Instructions._ 31import xiangshan.backend.Bundles.{DecodedInst, StaticInst} 32import xiangshan.backend.decode.isa.bitfield.XSInstBitFields 33import xiangshan.backend.fu.vector.Bundles.VType 34import yunsuan.VpermType 35 36import scala.collection.Seq 37 38trait VectorConstants { 39 val MAX_VLMUL = 8 40 val FP_TMP_REG_MV = 32 41 val VECTOR_TMP_REG_LMUL = 32 // 32~38 -> 7 42} 43 44class DecodeUnitCompIO(implicit p: Parameters) extends XSBundle { 45 val enq = new Bundle { val staticInst = Input(new StaticInst) } 46 val vtype = Input(new VType) 47 val isComplex = Input(Vec(DecodeWidth - 1, Bool())) 48 val validFromIBuf = Input(Vec(DecodeWidth, Bool())) 49 val readyFromRename = Input(Vec(RenameWidth, Bool())) 50 val deq = new Bundle { 51 val decodedInsts = Output(Vec(RenameWidth, new DecodedInst)) 52 val isVset = Output(Bool()) 53 val readyToIBuf = Output(Vec(DecodeWidth, Bool())) 54 val validToRename = Output(Vec(RenameWidth, Bool())) 55 val complexNum = Output(UInt(3.W)) 56 } 57 val csrCtrl = Input(new CustomCSRCtrlIO) 58} 59 60/** 61 * @author zly 62 */ 63class DecodeUnitComp()(implicit p : Parameters) extends XSModule with DecodeUnitConstants with VectorConstants { 64 val io = IO(new DecodeUnitCompIO) 65 66 val maxUopSize = MaxUopSize 67 //input bits 68 val staticInst = Wire(new StaticInst) 69 private val inst: XSInstBitFields = staticInst.asTypeOf(new XSInstBitFields) 70 71 staticInst := io.enq.staticInst 72 73 val src1 = Cat(0.U(1.W), inst.RS1) 74 val src2 = Cat(0.U(1.W), inst.RS2) 75 val dest = Cat(0.U(1.W), inst.RD) 76 val width = inst.RM //Vector LS eew 77 val eew = Cat(0.U(1.W), width(1, 0)) 78 79 //output bits 80 val decodedInsts = Wire(Vec(RenameWidth, new DecodedInst)) 81 val validToRename = Wire(Vec(RenameWidth, Bool())) 82 val readyToIBuf = Wire(Vec(DecodeWidth, Bool())) 83 val complexNum = Wire(UInt(3.W)) 84 85 //output of DecodeUnit 86 val decodedInsts_u = Wire(new DecodedInst) 87 val isVset_u = Wire(Bool()) 88 89 //pre decode 90 val simple = Module(new DecodeUnit) 91 simple.io.enq.ctrlFlow := staticInst 92 simple.io.enq.vtype := io.vtype 93 simple.io.csrCtrl := io.csrCtrl 94 decodedInsts_u := simple.io.deq.decodedInst 95 isVset_u := simple.io.deq.decodedInst.isVset 96 when(isVset_u) { 97 when(dest === 0.U && src1 === 0.U) { 98 decodedInsts_u.fuOpType := VSETOpType.keepVl(simple.io.deq.decodedInst.fuOpType) 99 }.elsewhen(src1 === 0.U) { 100 decodedInsts_u.fuOpType := VSETOpType.setVlmax(simple.io.deq.decodedInst.fuOpType) 101 } 102 when(io.vtype.illegal){ 103 decodedInsts_u.flushPipe := true.B 104 } 105 } 106 //Type of uop Div 107 val typeOfDiv = decodedInsts_u.uopSplitType 108 109 val sew = Cat(0.U(1.W), simple.io.enq.vtype.vsew) 110 val vlmul = simple.io.enq.vtype.vlmul 111 112 //LMUL 113 val lmul = MuxLookup(simple.io.enq.vtype.vlmul, 1.U(4.W), Array( 114 "b001".U -> 2.U, 115 "b010".U -> 4.U, 116 "b011".U -> 8.U 117 )) 118 val numOfUopVslide = MuxLookup(simple.io.enq.vtype.vlmul, 1.U(log2Up(maxUopSize+1).W), Array( 119 "b001".U -> 3.U, 120 "b010".U -> 10.U, 121 "b011".U -> 36.U 122 )) 123 val vemul : UInt = eew.asUInt + 1.U + vlmul.asUInt + ~sew.asUInt 124 val emul = MuxLookup(vemul, 1.U(4.W), Array( 125 "b001".U -> 2.U, 126 "b010".U -> 4.U, 127 "b011".U -> 8.U 128 )) //TODO : eew and emul illegal exception need to be handled 129 130 //number of uop 131 val numOfUop = MuxLookup(typeOfDiv, 1.U(log2Up(maxUopSize+1).W), Array( 132 UopSplitType.VEC_0XV -> 2.U, 133 UopSplitType.DIR -> Mux(dest =/= 0.U, 2.U, 134 Mux(src1 =/= 0.U, 1.U, 135 Mux(VSETOpType.isVsetvl(decodedInsts_u.fuOpType), 2.U, 1.U))), 136 UopSplitType.VEC_VVV -> lmul, 137 UopSplitType.VEC_EXT2 -> lmul, 138 UopSplitType.VEC_EXT4 -> lmul, 139 UopSplitType.VEC_EXT8 -> lmul, 140 UopSplitType.VEC_VVM -> lmul, 141 UopSplitType.VEC_VXM -> (lmul +& 1.U), 142 UopSplitType.VEC_VXV -> (lmul +& 1.U), 143 UopSplitType.VEC_VVW -> Cat(lmul, 0.U(1.W)), // lmul <= 4 144 UopSplitType.VEC_WVW -> Cat(lmul, 0.U(1.W)), // lmul <= 4 145 UopSplitType.VEC_VXW -> Cat(lmul, 1.U(1.W)), // lmul <= 4 146 UopSplitType.VEC_WXW -> Cat(lmul, 1.U(1.W)), // lmul <= 4 147 UopSplitType.VEC_WVV -> Cat(lmul, 0.U(1.W)), // lmul <= 4 148 UopSplitType.VEC_WXV -> Cat(lmul, 1.U(1.W)), // lmul <= 4 149 UopSplitType.VEC_SLIDE1UP -> (lmul +& 1.U), 150 UopSplitType.VEC_FSLIDE1UP -> lmul, 151 UopSplitType.VEC_SLIDE1DOWN -> Cat(lmul, 0.U(1.W)), 152 UopSplitType.VEC_FSLIDE1DOWN -> (Cat(lmul, 0.U(1.W)) -1.U), 153 UopSplitType.VEC_VRED -> lmul, 154 UopSplitType.VEC_SLIDEUP -> (numOfUopVslide + 1.U), 155 UopSplitType.VEC_ISLIDEUP -> numOfUopVslide, 156 UopSplitType.VEC_SLIDEDOWN -> (numOfUopVslide + 1.U), 157 UopSplitType.VEC_ISLIDEDOWN -> numOfUopVslide, 158 UopSplitType.VEC_M0X -> (lmul +& 1.U), 159 UopSplitType.VEC_MVV -> (Cat(lmul, 0.U(1.W)) -1.U), 160 UopSplitType.VEC_M0X_VFIRST -> 2.U, 161 UopSplitType.VEC_US_LD -> (emul +& 1.U), 162 )) 163 164 //uop div up to maxUopSize 165 val csBundle = Wire(Vec(maxUopSize, new DecodedInst)) 166 csBundle.map { case dst => 167 dst := decodedInsts_u 168 dst.firstUop := false.B 169 dst.lastUop := false.B 170 } 171 172 csBundle(0).numUops := numOfUop 173 csBundle(0).firstUop := true.B 174 csBundle(numOfUop - 1.U).lastUop := true.B 175 176 switch(typeOfDiv) { 177 is(UopSplitType.DIR) { 178 when(isVset_u) { 179 when(dest =/= 0.U) { 180 csBundle(0).fuType := FuType.vsetiwi.U 181 csBundle(0).fuOpType := VSETOpType.switchDest(decodedInsts_u.fuOpType) 182 csBundle(0).flushPipe := false.B 183 csBundle(0).rfWen := true.B 184 csBundle(0).vecWen := false.B 185 csBundle(1).ldest := VCONFIG_IDX.U 186 csBundle(1).rfWen := false.B 187 csBundle(1).vecWen := true.B 188 }.elsewhen(src1 =/= 0.U) { 189 csBundle(0).ldest := VCONFIG_IDX.U 190 }.elsewhen(VSETOpType.isVsetvli(decodedInsts_u.fuOpType)) { 191 csBundle(0).fuType := FuType.vsetfwf.U 192 csBundle(0).srcType(0) := SrcType.vp 193 csBundle(0).lsrc(0) := VCONFIG_IDX.U 194 }.elsewhen(VSETOpType.isVsetvl(decodedInsts_u.fuOpType)) { 195 csBundle(0).srcType(0) := SrcType.reg 196 csBundle(0).srcType(1) := SrcType.imm 197 csBundle(0).lsrc(1) := 0.U 198 csBundle(0).ldest := FP_TMP_REG_MV.U 199 csBundle(0).fuType := FuType.i2f.U 200 csBundle(0).rfWen := false.B 201 csBundle(0).fpWen := true.B 202 csBundle(0).vecWen := false.B 203 csBundle(0).fpu.isAddSub := false.B 204 csBundle(0).fpu.typeTagIn := FPU.D 205 csBundle(0).fpu.typeTagOut := FPU.D 206 csBundle(0).fpu.fromInt := true.B 207 csBundle(0).fpu.wflags := false.B 208 csBundle(0).fpu.fpWen := true.B 209 csBundle(0).fpu.div := false.B 210 csBundle(0).fpu.sqrt := false.B 211 csBundle(0).fpu.fcvt := false.B 212 csBundle(0).flushPipe := false.B 213 csBundle(1).fuType := FuType.vsetfwf.U 214 csBundle(1).srcType(0) := SrcType.vp 215 csBundle(1).lsrc(0) := VCONFIG_IDX.U 216 csBundle(1).srcType(1) := SrcType.fp 217 csBundle(1).lsrc(1) := FP_TMP_REG_MV.U 218 csBundle(1).ldest := VCONFIG_IDX.U 219 } 220 } 221 } 222 is(UopSplitType.VEC_VVV) { 223 for (i <- 0 until MAX_VLMUL) { 224 csBundle(i).lsrc(0) := src1 + i.U 225 csBundle(i).lsrc(1) := src2 + i.U 226 csBundle(i).lsrc(2) := dest + i.U 227 csBundle(i).ldest := dest + i.U 228 csBundle(i).uopIdx := i.U 229 } 230 } 231 is(UopSplitType.VEC_EXT2) { 232 for (i <- 0 until MAX_VLMUL / 2) { 233 csBundle(2 * i).lsrc(1) := src2 + i.U 234 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 235 csBundle(2 * i).ldest := dest + (2 * i).U 236 csBundle(2 * i).uopIdx := (2 * i).U 237 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 238 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 239 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 240 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 241 } 242 } 243 is(UopSplitType.VEC_EXT4) { 244 for (i <- 0 until MAX_VLMUL / 4) { 245 csBundle(4 * i).lsrc(1) := src2 + i.U 246 csBundle(4 * i).lsrc(2) := dest + (4 * i).U 247 csBundle(4 * i).ldest := dest + (4 * i).U 248 csBundle(4 * i).uopIdx := (4 * i).U 249 csBundle(4 * i + 1).lsrc(1) := src2 + i.U 250 csBundle(4 * i + 1).lsrc(2) := dest + (4 * i + 1).U 251 csBundle(4 * i + 1).ldest := dest + (4 * i + 1).U 252 csBundle(4 * i + 1).uopIdx := (4 * i + 1).U 253 csBundle(4 * i + 2).lsrc(1) := src2 + i.U 254 csBundle(4 * i + 2).lsrc(2) := dest + (4 * i + 2).U 255 csBundle(4 * i + 2).ldest := dest + (4 * i + 2).U 256 csBundle(4 * i + 2).uopIdx := (4 * i + 2).U 257 csBundle(4 * i + 3).lsrc(1) := src2 + i.U 258 csBundle(4 * i + 3).lsrc(2) := dest + (4 * i + 3).U 259 csBundle(4 * i + 3).ldest := dest + (4 * i + 3).U 260 csBundle(4 * i + 3).uopIdx := (4 * i + 3).U 261 } 262 } 263 is(UopSplitType.VEC_EXT8) { 264 for (i <- 0 until MAX_VLMUL) { 265 csBundle(i).lsrc(1) := src2 266 csBundle(i).lsrc(2) := dest + i.U 267 csBundle(i).ldest := dest + i.U 268 csBundle(i).uopIdx := i.U 269 } 270 } 271 is(UopSplitType.VEC_0XV) { 272 /* 273 FMV.D.X 274 */ 275 csBundle(0).srcType(0) := SrcType.reg 276 csBundle(0).srcType(1) := SrcType.imm 277 csBundle(0).lsrc(1) := 0.U 278 csBundle(0).ldest := FP_TMP_REG_MV.U 279 csBundle(0).fuType := FuType.i2f.U 280 csBundle(0).rfWen := false.B 281 csBundle(0).fpWen := true.B 282 csBundle(0).vecWen := false.B 283 csBundle(0).fpu.isAddSub := false.B 284 csBundle(0).fpu.typeTagIn := FPU.D 285 csBundle(0).fpu.typeTagOut := FPU.D 286 csBundle(0).fpu.fromInt := true.B 287 csBundle(0).fpu.wflags := false.B 288 csBundle(0).fpu.fpWen := true.B 289 csBundle(0).fpu.div := false.B 290 csBundle(0).fpu.sqrt := false.B 291 csBundle(0).fpu.fcvt := false.B 292 /* 293 vfmv.s.f 294 */ 295 csBundle(1).srcType(0) := SrcType.fp 296 csBundle(1).srcType(1) := SrcType.vp 297 csBundle(1).srcType(2) := SrcType.vp 298 csBundle(1).lsrc(0) := FP_TMP_REG_MV.U 299 csBundle(1).lsrc(1) := 0.U 300 csBundle(1).lsrc(2) := dest 301 csBundle(1).ldest := dest 302 csBundle(1).fuType := FuType.vppu.U 303 csBundle(1).fuOpType := VpermType.dummy 304 csBundle(1).rfWen := false.B 305 csBundle(1).fpWen := false.B 306 csBundle(1).vecWen := true.B 307 } 308 is(UopSplitType.VEC_VXV) { 309 /* 310 FMV.D.X 311 */ 312 csBundle(0).srcType(0) := SrcType.reg 313 csBundle(0).srcType(1) := SrcType.imm 314 csBundle(0).lsrc(1) := 0.U 315 csBundle(0).ldest := FP_TMP_REG_MV.U 316 csBundle(0).fuType := FuType.i2f.U 317 csBundle(0).rfWen := false.B 318 csBundle(0).fpWen := true.B 319 csBundle(0).vecWen := false.B 320 csBundle(0).fpu.isAddSub := false.B 321 csBundle(0).fpu.typeTagIn := FPU.D 322 csBundle(0).fpu.typeTagOut := FPU.D 323 csBundle(0).fpu.fromInt := true.B 324 csBundle(0).fpu.wflags := false.B 325 csBundle(0).fpu.fpWen := true.B 326 csBundle(0).fpu.div := false.B 327 csBundle(0).fpu.sqrt := false.B 328 csBundle(0).fpu.fcvt := false.B 329 /* 330 LMUL 331 */ 332 for (i <- 0 until MAX_VLMUL) { 333 csBundle(i + 1).srcType(0) := SrcType.fp 334 csBundle(i + 1).lsrc(0) := FP_TMP_REG_MV.U 335 csBundle(i + 1).lsrc(1) := src2 + i.U 336 csBundle(i + 1).lsrc(2) := dest + i.U 337 csBundle(i + 1).ldest := dest + i.U 338 csBundle(i + 1).uopIdx := i.U 339 } 340 } 341 is(UopSplitType.VEC_VVW) { 342 for (i <- 0 until MAX_VLMUL / 2) { 343 csBundle(2 * i).lsrc(0) := src1 + i.U 344 csBundle(2 * i).lsrc(1) := src2 + i.U 345 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 346 csBundle(2 * i).ldest := dest + (2 * i).U 347 csBundle(2 * i).uopIdx := (2 * i).U 348 csBundle(2 * i + 1).lsrc(0) := src1 + i.U 349 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 350 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 351 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 352 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 353 } 354 } 355 is(UopSplitType.VEC_WVW) { 356 for (i <- 0 until MAX_VLMUL / 2) { 357 csBundle(2 * i).lsrc(0) := src1 + i.U 358 csBundle(2 * i).lsrc(1) := src2 + (2 * i).U 359 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 360 csBundle(2 * i).ldest := dest + (2 * i).U 361 csBundle(2 * i).uopIdx := (2 * i).U 362 csBundle(2 * i + 1).lsrc(0) := src1 + i.U 363 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i + 1).U 364 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 365 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 366 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 367 } 368 } 369 is(UopSplitType.VEC_VXW) { 370 /* 371 FMV.D.X 372 */ 373 csBundle(0).srcType(0) := SrcType.reg 374 csBundle(0).srcType(1) := SrcType.imm 375 csBundle(0).lsrc(1) := 0.U 376 csBundle(0).ldest := FP_TMP_REG_MV.U 377 csBundle(0).fuType := FuType.i2f.U 378 csBundle(0).rfWen := false.B 379 csBundle(0).fpWen := true.B 380 csBundle(0).vecWen := false.B 381 csBundle(0).fpu.isAddSub := false.B 382 csBundle(0).fpu.typeTagIn := FPU.D 383 csBundle(0).fpu.typeTagOut := FPU.D 384 csBundle(0).fpu.fromInt := true.B 385 csBundle(0).fpu.wflags := false.B 386 csBundle(0).fpu.fpWen := true.B 387 csBundle(0).fpu.div := false.B 388 csBundle(0).fpu.sqrt := false.B 389 csBundle(0).fpu.fcvt := false.B 390 391 for (i <- 0 until MAX_VLMUL / 2) { 392 csBundle(2 * i + 1).srcType(0) := SrcType.fp 393 csBundle(2 * i + 1).lsrc(0) := FP_TMP_REG_MV.U 394 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 395 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i).U 396 csBundle(2 * i + 1).ldest := dest + (2 * i).U 397 csBundle(2 * i + 1).uopIdx := (2 * i).U 398 csBundle(2 * i + 2).srcType(0) := SrcType.fp 399 csBundle(2 * i + 2).lsrc(0) := FP_TMP_REG_MV.U 400 csBundle(2 * i + 2).lsrc(1) := src2 + i.U 401 csBundle(2 * i + 2).lsrc(2) := dest + (2 * i + 1).U 402 csBundle(2 * i + 2).ldest := dest + (2 * i + 1).U 403 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 404 } 405 } 406 is(UopSplitType.VEC_WXW) { 407 /* 408 FMV.D.X 409 */ 410 csBundle(0).srcType(0) := SrcType.reg 411 csBundle(0).srcType(1) := SrcType.imm 412 csBundle(0).lsrc(1) := 0.U 413 csBundle(0).ldest := FP_TMP_REG_MV.U 414 csBundle(0).fuType := FuType.i2f.U 415 csBundle(0).rfWen := false.B 416 csBundle(0).fpWen := true.B 417 csBundle(0).vecWen := false.B 418 csBundle(0).fpu.isAddSub := false.B 419 csBundle(0).fpu.typeTagIn := FPU.D 420 csBundle(0).fpu.typeTagOut := FPU.D 421 csBundle(0).fpu.fromInt := true.B 422 csBundle(0).fpu.wflags := false.B 423 csBundle(0).fpu.fpWen := true.B 424 csBundle(0).fpu.div := false.B 425 csBundle(0).fpu.sqrt := false.B 426 csBundle(0).fpu.fcvt := false.B 427 428 for (i <- 0 until MAX_VLMUL / 2) { 429 csBundle(2 * i + 1).srcType(0) := SrcType.fp 430 csBundle(2 * i + 1).lsrc(0) := FP_TMP_REG_MV.U 431 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i).U 432 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i).U 433 csBundle(2 * i + 1).ldest := dest + (2 * i).U 434 csBundle(2 * i + 1).uopIdx := (2 * i).U 435 csBundle(2 * i + 2).srcType(0) := SrcType.fp 436 csBundle(2 * i + 2).lsrc(0) := FP_TMP_REG_MV.U 437 csBundle(2 * i + 2).lsrc(1) := src2 + (2 * i + 1).U 438 csBundle(2 * i + 2).lsrc(2) := dest + (2 * i + 1).U 439 csBundle(2 * i + 2).ldest := dest + (2 * i + 1).U 440 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 441 } 442 } 443 is(UopSplitType.VEC_WVV) { 444 for (i <- 0 until MAX_VLMUL / 2) { 445 446 csBundle(2 * i).lsrc(0) := src1 + i.U 447 csBundle(2 * i).lsrc(1) := src2 + (2 * i).U 448 csBundle(2 * i).lsrc(2) := dest + i.U 449 csBundle(2 * i).ldest := dest + i.U 450 csBundle(2 * i).uopIdx := (2 * i).U 451 csBundle(2 * i + 1).lsrc(0) := src1 + i.U 452 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i + 1).U 453 csBundle(2 * i + 1).lsrc(2) := dest + i.U 454 csBundle(2 * i + 1).ldest := dest + i.U 455 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 456 } 457 } 458 is(UopSplitType.VEC_WXV) { 459 /* 460 FMV.D.X 461 */ 462 csBundle(0).srcType(0) := SrcType.reg 463 csBundle(0).srcType(1) := SrcType.imm 464 csBundle(0).lsrc(1) := 0.U 465 csBundle(0).ldest := FP_TMP_REG_MV.U 466 csBundle(0).fuType := FuType.i2f.U 467 csBundle(0).rfWen := false.B 468 csBundle(0).fpWen := true.B 469 csBundle(0).vecWen := false.B 470 csBundle(0).fpu.isAddSub := false.B 471 csBundle(0).fpu.typeTagIn := FPU.D 472 csBundle(0).fpu.typeTagOut := FPU.D 473 csBundle(0).fpu.fromInt := true.B 474 csBundle(0).fpu.wflags := false.B 475 csBundle(0).fpu.fpWen := true.B 476 csBundle(0).fpu.div := false.B 477 csBundle(0).fpu.sqrt := false.B 478 csBundle(0).fpu.fcvt := false.B 479 480 for (i <- 0 until MAX_VLMUL / 2) { 481 csBundle(2 * i + 1).srcType(0) := SrcType.fp 482 csBundle(2 * i + 1).lsrc(0) := FP_TMP_REG_MV.U 483 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i).U 484 csBundle(2 * i + 1).lsrc(2) := dest + i.U 485 csBundle(2 * i + 1).ldest := dest + i.U 486 csBundle(2 * i + 1).uopIdx := (2 * i).U 487 csBundle(2 * i + 2).srcType(0) := SrcType.fp 488 csBundle(2 * i + 2).lsrc(0) := FP_TMP_REG_MV.U 489 csBundle(2 * i + 2).lsrc(1) := src2 + (2 * i + 1).U 490 csBundle(2 * i + 2).lsrc(2) := dest + i.U 491 csBundle(2 * i + 2).ldest := dest + i.U 492 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 493 } 494 } 495 is(UopSplitType.VEC_VVM) { 496 csBundle(0).lsrc(2) := dest 497 csBundle(0).ldest := dest 498 csBundle(0).uopIdx := 0.U 499 for (i <- 1 until MAX_VLMUL) { 500 csBundle(i).lsrc(0) := src1 + i.U 501 csBundle(i).lsrc(1) := src2 + i.U 502 csBundle(i).lsrc(2) := dest 503 csBundle(i).ldest := dest 504 csBundle(i).uopIdx := i.U 505 } 506 csBundle(numOfUop - 1.U).ldest := dest 507 } 508 is(UopSplitType.VEC_VXM) { 509 /* 510 FMV.D.X 511 */ 512 csBundle(0).srcType(0) := SrcType.reg 513 csBundle(0).srcType(1) := SrcType.imm 514 csBundle(0).lsrc(1) := 0.U 515 csBundle(0).ldest := FP_TMP_REG_MV.U 516 csBundle(0).fuType := FuType.i2f.U 517 csBundle(0).rfWen := false.B 518 csBundle(0).fpWen := true.B 519 csBundle(0).vecWen := false.B 520 csBundle(0).fpu.isAddSub := false.B 521 csBundle(0).fpu.typeTagIn := FPU.D 522 csBundle(0).fpu.typeTagOut := FPU.D 523 csBundle(0).fpu.fromInt := true.B 524 csBundle(0).fpu.wflags := false.B 525 csBundle(0).fpu.fpWen := true.B 526 csBundle(0).fpu.div := false.B 527 csBundle(0).fpu.sqrt := false.B 528 csBundle(0).fpu.fcvt := false.B 529 //LMUL 530 csBundle(1).srcType(0) := SrcType.fp 531 csBundle(1).lsrc(0) := FP_TMP_REG_MV.U 532 csBundle(1).lsrc(2) := dest 533 csBundle(1).ldest := dest 534 csBundle(1).uopIdx := 0.U 535 for (i <- 1 until MAX_VLMUL) { 536 csBundle(i + 1).srcType(0) := SrcType.fp 537 csBundle(i + 1).lsrc(0) := FP_TMP_REG_MV.U 538 csBundle(i + 1).lsrc(1) := src2 + i.U 539 csBundle(i + 1).lsrc(2) := dest 540 csBundle(i + 1).ldest := dest 541 csBundle(i + 1).uopIdx := i.U 542 } 543 csBundle(numOfUop - 1.U).ldest := dest 544 } 545 is(UopSplitType.VEC_SLIDE1UP) { 546 /* 547 FMV.D.X 548 */ 549 csBundle(0).srcType(0) := SrcType.reg 550 csBundle(0).srcType(1) := SrcType.imm 551 csBundle(0).lsrc(1) := 0.U 552 csBundle(0).ldest := FP_TMP_REG_MV.U 553 csBundle(0).fuType := FuType.i2f.U 554 csBundle(0).rfWen := false.B 555 csBundle(0).fpWen := true.B 556 csBundle(0).vecWen := false.B 557 csBundle(0).fpu.isAddSub := false.B 558 csBundle(0).fpu.typeTagIn := FPU.D 559 csBundle(0).fpu.typeTagOut := FPU.D 560 csBundle(0).fpu.fromInt := true.B 561 csBundle(0).fpu.wflags := false.B 562 csBundle(0).fpu.fpWen := true.B 563 csBundle(0).fpu.div := false.B 564 csBundle(0).fpu.sqrt := false.B 565 csBundle(0).fpu.fcvt := false.B 566 //LMUL 567 csBundle(1).srcType(0) := SrcType.fp 568 csBundle(1).lsrc(0) := FP_TMP_REG_MV.U 569 csBundle(1).lsrc(2) := dest 570 csBundle(1).ldest := dest 571 csBundle(1).uopIdx := 0.U 572 for (i <- 1 until MAX_VLMUL) { 573 csBundle(i + 1).srcType(0) := SrcType.vp 574 csBundle(i + 1).lsrc(0) := src2 + (i - 1).U 575 csBundle(i + 1).lsrc(1) := src2 + i.U 576 csBundle(i + 1).lsrc(2) := dest + i.U 577 csBundle(i + 1).ldest := dest + i.U 578 csBundle(i + 1).uopIdx := i.U 579 } 580 } 581 is(UopSplitType.VEC_FSLIDE1UP) { 582 //LMUL 583 csBundle(0).srcType(0) := SrcType.fp 584 csBundle(0).lsrc(0) := src1 585 csBundle(0).lsrc(1) := src2 586 csBundle(0).lsrc(2) := dest 587 csBundle(0).ldest := dest 588 csBundle(0).uopIdx := 0.U 589 for (i <- 1 until MAX_VLMUL) { 590 csBundle(i).srcType(0) := SrcType.vp 591 csBundle(i).lsrc(0) := src2 + (i - 1).U 592 csBundle(i).lsrc(1) := src2 + i.U 593 csBundle(i).lsrc(2) := dest + i.U 594 csBundle(i).ldest := dest + i.U 595 csBundle(i).uopIdx := i.U 596 } 597 } 598 is(UopSplitType.VEC_SLIDE1DOWN) { // lmul+lmul = 16 599 /* 600 FMV.D.X 601 */ 602 csBundle(0).srcType(0) := SrcType.reg 603 csBundle(0).srcType(1) := SrcType.imm 604 csBundle(0).lsrc(1) := 0.U 605 csBundle(0).ldest := FP_TMP_REG_MV.U 606 csBundle(0).fuType := FuType.i2f.U 607 csBundle(0).rfWen := false.B 608 csBundle(0).fpWen := true.B 609 csBundle(0).vecWen := false.B 610 csBundle(0).fpu.isAddSub := false.B 611 csBundle(0).fpu.typeTagIn := FPU.D 612 csBundle(0).fpu.typeTagOut := FPU.D 613 csBundle(0).fpu.fromInt := true.B 614 csBundle(0).fpu.wflags := false.B 615 csBundle(0).fpu.fpWen := true.B 616 csBundle(0).fpu.div := false.B 617 csBundle(0).fpu.sqrt := false.B 618 csBundle(0).fpu.fcvt := false.B 619 //LMUL 620 for (i <- 0 until MAX_VLMUL) { 621 csBundle(2 * i + 1).srcType(0) := SrcType.vp 622 csBundle(2 * i + 1).srcType(1) := SrcType.vp 623 csBundle(2 * i + 1).lsrc(0) := src2 + (i + 1).U 624 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 625 csBundle(2 * i + 1).lsrc(2) := dest + i.U 626 csBundle(2 * i + 1).ldest := VECTOR_TMP_REG_LMUL.U 627 csBundle(2 * i + 1).uopIdx := (2 * i).U 628 if (2 * i + 2 < MAX_VLMUL * 2) { 629 csBundle(2 * i + 2).srcType(0) := SrcType.fp 630 csBundle(2 * i + 2).lsrc(0) := FP_TMP_REG_MV.U 631 // csBundle(2 * i + 2).lsrc(1) := src2 + i.U // DontCare 632 csBundle(2 * i + 2).lsrc(2) := VECTOR_TMP_REG_LMUL.U 633 csBundle(2 * i + 2).ldest := dest + i.U 634 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 635 } 636 } 637 csBundle(numOfUop - 1.U).srcType(0) := SrcType.fp 638 csBundle(numOfUop - 1.U).lsrc(0) := FP_TMP_REG_MV.U 639 csBundle(numOfUop - 1.U).ldest := dest + lmul - 1.U 640 } 641 is(UopSplitType.VEC_FSLIDE1DOWN) { 642 //LMUL 643 for (i <- 0 until MAX_VLMUL) { 644 csBundle(2 * i).srcType(0) := SrcType.vp 645 csBundle(2 * i).srcType(1) := SrcType.vp 646 csBundle(2 * i).lsrc(0) := src2 + (i + 1).U 647 csBundle(2 * i).lsrc(1) := src2 + i.U 648 csBundle(2 * i).lsrc(2) := dest + i.U 649 csBundle(2 * i).ldest := VECTOR_TMP_REG_LMUL.U 650 csBundle(2 * i).uopIdx := (2 * i).U 651 csBundle(2 * i + 1).srcType(0) := SrcType.fp 652 csBundle(2 * i + 1).lsrc(0) := src1 653 csBundle(2 * i + 1).lsrc(2) := VECTOR_TMP_REG_LMUL.U 654 csBundle(2 * i + 1).ldest := dest + i.U 655 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 656 } 657 csBundle(numOfUop - 1.U).srcType(0) := SrcType.fp 658 csBundle(numOfUop - 1.U).lsrc(0) := src1 659 csBundle(numOfUop - 1.U).ldest := dest + lmul - 1.U 660 } 661 is(UopSplitType.VEC_VRED) { 662 when(simple.io.enq.vtype.vlmul === "b001".U) { 663 csBundle(0).srcType(2) := SrcType.DC 664 csBundle(0).lsrc(0) := src2 + 1.U 665 csBundle(0).lsrc(1) := src2 666 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 667 csBundle(0).uopIdx := 0.U 668 } 669 when(simple.io.enq.vtype.vlmul === "b010".U) { 670 csBundle(0).srcType(2) := SrcType.DC 671 csBundle(0).lsrc(0) := src2 + 1.U 672 csBundle(0).lsrc(1) := src2 673 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 674 csBundle(0).uopIdx := 0.U 675 676 csBundle(1).srcType(2) := SrcType.DC 677 csBundle(1).lsrc(0) := src2 + 3.U 678 csBundle(1).lsrc(1) := src2 + 2.U 679 csBundle(1).ldest := (VECTOR_TMP_REG_LMUL + 1).U 680 csBundle(1).uopIdx := 1.U 681 682 csBundle(2).srcType(2) := SrcType.DC 683 csBundle(2).lsrc(0) := (VECTOR_TMP_REG_LMUL + 1).U 684 csBundle(2).lsrc(1) := VECTOR_TMP_REG_LMUL.U 685 csBundle(2).ldest := (VECTOR_TMP_REG_LMUL + 2).U 686 csBundle(2).uopIdx := 2.U 687 } 688 when(simple.io.enq.vtype.vlmul === "b011".U) { 689 for (i <- 0 until MAX_VLMUL) { 690 if (i < MAX_VLMUL - MAX_VLMUL / 2) { 691 csBundle(i).lsrc(0) := src2 + (i * 2 + 1).U 692 csBundle(i).lsrc(1) := src2 + (i * 2).U 693 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 694 } else if (i < MAX_VLMUL - MAX_VLMUL / 4) { 695 csBundle(i).lsrc(0) := (VECTOR_TMP_REG_LMUL + (i - MAX_VLMUL / 2) * 2 + 1).U 696 csBundle(i).lsrc(1) := (VECTOR_TMP_REG_LMUL + (i - MAX_VLMUL / 2) * 2).U 697 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 698 } else if (i < MAX_VLMUL - MAX_VLMUL / 8) { 699 csBundle(6).lsrc(0) := (VECTOR_TMP_REG_LMUL + 5).U 700 csBundle(6).lsrc(1) := (VECTOR_TMP_REG_LMUL + 4).U 701 csBundle(6).ldest := (VECTOR_TMP_REG_LMUL + 6).U 702 } 703 csBundle(i).srcType(2) := SrcType.DC 704 csBundle(i).uopIdx := i.U 705 } 706 } 707 when(simple.io.enq.vtype.vlmul.orR()) { 708 csBundle(numOfUop - 1.U).srcType(2) := SrcType.vp 709 csBundle(numOfUop - 1.U).lsrc(0) := src1 710 csBundle(numOfUop - 1.U).lsrc(1) := VECTOR_TMP_REG_LMUL.U + numOfUop - 2.U 711 csBundle(numOfUop - 1.U).lsrc(2) := dest 712 csBundle(numOfUop - 1.U).ldest := dest 713 csBundle(numOfUop - 1.U).uopIdx := numOfUop - 1.U 714 } 715 } 716 717 is(UopSplitType.VEC_SLIDEUP) { 718 // FMV.D.X 719 csBundle(0).srcType(0) := SrcType.reg 720 csBundle(0).srcType(1) := SrcType.imm 721 csBundle(0).lsrc(1) := 0.U 722 csBundle(0).ldest := FP_TMP_REG_MV.U 723 csBundle(0).fuType := FuType.i2f.U 724 csBundle(0).rfWen := false.B 725 csBundle(0).fpWen := true.B 726 csBundle(0).vecWen := false.B 727 csBundle(0).fpu.isAddSub := false.B 728 csBundle(0).fpu.typeTagIn := FPU.D 729 csBundle(0).fpu.typeTagOut := FPU.D 730 csBundle(0).fpu.fromInt := true.B 731 csBundle(0).fpu.wflags := false.B 732 csBundle(0).fpu.fpWen := true.B 733 csBundle(0).fpu.div := false.B 734 csBundle(0).fpu.sqrt := false.B 735 csBundle(0).fpu.fcvt := false.B 736 // LMUL 737 for (i <- 0 until MAX_VLMUL) 738 for (j <- 0 to i) { 739 val old_vd = if (j == 0) { 740 dest + i.U 741 } else (VECTOR_TMP_REG_LMUL + j - 1).U 742 val vd = if (j == i) { 743 dest + i.U 744 } else (VECTOR_TMP_REG_LMUL + j).U 745 csBundle(i * (i + 1) / 2 + j + 1).srcType(0) := SrcType.fp 746 csBundle(i * (i + 1) / 2 + j + 1).lsrc(0) := FP_TMP_REG_MV.U 747 csBundle(i * (i + 1) / 2 + j + 1).lsrc(1) := src2 + j.U 748 csBundle(i * (i + 1) / 2 + j + 1).lsrc(2) := old_vd 749 csBundle(i * (i + 1) / 2 + j + 1).ldest := vd 750 csBundle(i * (i + 1) / 2 + j + 1).uopIdx := (i * (i + 1) / 2 + j).U 751 } 752 } 753 754 is(UopSplitType.VEC_ISLIDEUP) { 755 // LMUL 756 for (i <- 0 until MAX_VLMUL) 757 for (j <- 0 to i) { 758 val old_vd = if (j == 0) { 759 dest + i.U 760 } else (VECTOR_TMP_REG_LMUL + j - 1).U 761 val vd = if (j == i) { 762 dest + i.U 763 } else (VECTOR_TMP_REG_LMUL + j).U 764 csBundle(i * (i + 1) / 2 + j).lsrc(1) := src2 + j.U 765 csBundle(i * (i + 1) / 2 + j).lsrc(2) := old_vd 766 csBundle(i * (i + 1) / 2 + j).ldest := vd 767 csBundle(i * (i + 1) / 2 + j).uopIdx := (i * (i + 1) / 2 + j).U 768 } 769 } 770 771 is(UopSplitType.VEC_SLIDEDOWN) { 772 // FMV.D.X 773 csBundle(0).srcType(0) := SrcType.reg 774 csBundle(0).srcType(1) := SrcType.imm 775 csBundle(0).lsrc(1) := 0.U 776 csBundle(0).ldest := FP_TMP_REG_MV.U 777 csBundle(0).fuType := FuType.i2f.U 778 csBundle(0).rfWen := false.B 779 csBundle(0).fpWen := true.B 780 csBundle(0).vecWen := false.B 781 csBundle(0).fpu.isAddSub := false.B 782 csBundle(0).fpu.typeTagIn := FPU.D 783 csBundle(0).fpu.typeTagOut := FPU.D 784 csBundle(0).fpu.fromInt := true.B 785 csBundle(0).fpu.wflags := false.B 786 csBundle(0).fpu.fpWen := true.B 787 csBundle(0).fpu.div := false.B 788 csBundle(0).fpu.sqrt := false.B 789 csBundle(0).fpu.fcvt := false.B 790 // LMUL 791 for (i <- 0 until MAX_VLMUL) 792 for (j <- (0 to i).reverse) { 793 when(i.U < lmul) { 794 val old_vd = if (j == 0) { 795 dest + lmul - 1.U - i.U 796 } else (VECTOR_TMP_REG_LMUL + j - 1).U 797 val vd = if (j == i) { 798 dest + lmul - 1.U - i.U 799 } else (VECTOR_TMP_REG_LMUL + j).U 800 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).srcType(0) := SrcType.fp 801 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).lsrc(0) := FP_TMP_REG_MV.U 802 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).lsrc(1) := src2 + lmul - 1.U - j.U 803 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).lsrc(2) := old_vd 804 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).ldest := vd 805 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).uopIdx := numOfUop - (i * (i + 1) / 2 + i - j + 2).U 806 } 807 } 808 } 809 810 is(UopSplitType.VEC_ISLIDEDOWN) { 811 // LMUL 812 for (i <- 0 until MAX_VLMUL) 813 for (j <- (0 to i).reverse) { 814 when(i.U < lmul) { 815 val old_vd = if (j == 0) { 816 dest + lmul - 1.U - i.U 817 } else (VECTOR_TMP_REG_LMUL + j - 1).U 818 val vd = if (j == i) { 819 dest + lmul - 1.U - i.U 820 } else (VECTOR_TMP_REG_LMUL + j).U 821 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).lsrc(1) := src2 + lmul - 1.U - j.U 822 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).lsrc(2) := old_vd 823 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).ldest := vd 824 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).uopIdx := numOfUop - (i * (i + 1) / 2 + i - j + 1).U 825 } 826 } 827 } 828 829 is(UopSplitType.VEC_M0X) { 830 // LMUL 831 for (i <- 0 until MAX_VLMUL) { 832 val srcType0 = if (i == 0) SrcType.DC else SrcType.vp 833 val ldest = (VECTOR_TMP_REG_LMUL + i).U 834 csBundle(i).srcType(0) := srcType0 835 csBundle(i).srcType(1) := SrcType.vp 836 csBundle(i).rfWen := false.B 837 csBundle(i).vecWen := true.B 838 csBundle(i).lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 839 csBundle(i).lsrc(1) := src2 840 // csBundle(i).lsrc(2) := dest + i.U DontCare 841 csBundle(i).ldest := ldest 842 csBundle(i).uopIdx := i.U 843 } 844 csBundle(lmul - 1.U).vecWen := false.B 845 csBundle(lmul - 1.U).fpWen := true.B 846 csBundle(lmul - 1.U).ldest := FP_TMP_REG_MV.U 847 // FMV_X_D 848 csBundle(lmul).srcType(0) := SrcType.fp 849 csBundle(lmul).srcType(1) := SrcType.imm 850 csBundle(lmul).lsrc(0) := FP_TMP_REG_MV.U 851 csBundle(lmul).lsrc(1) := 0.U 852 csBundle(lmul).ldest := dest 853 csBundle(lmul).fuType := FuType.fmisc.U 854 csBundle(lmul).rfWen := true.B 855 csBundle(lmul).fpWen := false.B 856 csBundle(lmul).vecWen := false.B 857 csBundle(lmul).fpu.isAddSub := false.B 858 csBundle(lmul).fpu.typeTagIn := FPU.D 859 csBundle(lmul).fpu.typeTagOut := FPU.D 860 csBundle(lmul).fpu.fromInt := false.B 861 csBundle(lmul).fpu.wflags := false.B 862 csBundle(lmul).fpu.fpWen := false.B 863 csBundle(lmul).fpu.div := false.B 864 csBundle(lmul).fpu.sqrt := false.B 865 csBundle(lmul).fpu.fcvt := false.B 866 } 867 868 is(UopSplitType.VEC_MVV) { 869 // LMUL 870 for (i <- 0 until MAX_VLMUL) { 871 val srcType0 = if (i == 0) SrcType.DC else SrcType.vp 872 csBundle(i * 2 + 0).srcType(0) := srcType0 873 csBundle(i * 2 + 0).srcType(1) := SrcType.vp 874 csBundle(i * 2 + 0).lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 875 csBundle(i * 2 + 0).lsrc(1) := src2 876 csBundle(i * 2 + 0).lsrc(2) := dest + i.U 877 csBundle(i * 2 + 0).ldest := dest + i.U 878 csBundle(i * 2 + 0).uopIdx := (i * 2 + 0).U 879 880 csBundle(i * 2 + 1).srcType(0) := srcType0 881 csBundle(i * 2 + 1).srcType(1) := SrcType.vp 882 csBundle(i * 2 + 1).lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 883 csBundle(i * 2 + 1).lsrc(1) := src2 884 // csBundle(i).lsrc(2) := dest + i.U DontCare 885 csBundle(i * 2 + 1).ldest := (VECTOR_TMP_REG_LMUL + i).U 886 csBundle(i * 2 + 1).uopIdx := (i * 2 + 1).U 887 } 888 } 889 890 is(UopSplitType.VEC_M0X_VFIRST) { 891 // LMUL 892 csBundle(0).rfWen := false.B 893 csBundle(0).fpWen := true.B 894 csBundle(0).ldest := FP_TMP_REG_MV.U 895 // FMV_X_D 896 csBundle(1).srcType(0) := SrcType.fp 897 csBundle(1).srcType(1) := SrcType.imm 898 csBundle(1).lsrc(0) := FP_TMP_REG_MV.U 899 csBundle(1).lsrc(1) := 0.U 900 csBundle(1).ldest := dest 901 csBundle(1).fuType := FuType.fmisc.U 902 csBundle(1).rfWen := true.B 903 csBundle(1).fpWen := false.B 904 csBundle(1).vecWen := false.B 905 csBundle(1).fpu.isAddSub := false.B 906 csBundle(1).fpu.typeTagIn := FPU.D 907 csBundle(1).fpu.typeTagOut := FPU.D 908 csBundle(1).fpu.fromInt := false.B 909 csBundle(1).fpu.wflags := false.B 910 csBundle(1).fpu.fpWen := false.B 911 csBundle(1).fpu.div := false.B 912 csBundle(1).fpu.sqrt := false.B 913 csBundle(1).fpu.fcvt := false.B 914 } 915 is(UopSplitType.VEC_US_LD) { 916 /* 917 FMV.D.X 918 */ 919 csBundle(0).srcType(0) := SrcType.reg 920 csBundle(0).srcType(1) := SrcType.imm 921 csBundle(0).lsrc(1) := 0.U 922 csBundle(0).ldest := FP_TMP_REG_MV.U 923 csBundle(0).fuType := FuType.i2f.U 924 csBundle(0).rfWen := false.B 925 csBundle(0).fpWen := true.B 926 csBundle(0).vecWen := false.B 927 csBundle(0).fpu.isAddSub := false.B 928 csBundle(0).fpu.typeTagIn := FPU.D 929 csBundle(0).fpu.typeTagOut := FPU.D 930 csBundle(0).fpu.fromInt := true.B 931 csBundle(0).fpu.wflags := false.B 932 csBundle(0).fpu.fpWen := true.B 933 csBundle(0).fpu.div := false.B 934 csBundle(0).fpu.sqrt := false.B 935 csBundle(0).fpu.fcvt := false.B 936 //LMUL 937 for (i <- 0 until MAX_VLMUL) { 938 csBundle(i + 1).srcType(0) := SrcType.fp 939 csBundle(i + 1).lsrc(0) := FP_TMP_REG_MV.U 940 csBundle(i + 1).ldest := dest + i.U 941 csBundle(i + 1).uopIdx := i.U 942 } 943 } 944 } 945 946 //uops dispatch 947 val normal :: ext :: Nil = Enum(2) 948 val stateReg = RegInit(normal) 949 val uopRes = RegInit(0.U) 950 951 //readyFromRename Counter 952 val readyCounter = PriorityMuxDefault(io.readyFromRename.map(x => !x).zip((0 to (RenameWidth - 1)).map(_.U)), RenameWidth.U) 953 954 switch(stateReg) { 955 is(normal) { 956 stateReg := Mux(io.validFromIBuf(0) && (numOfUop > readyCounter) && (readyCounter =/= 0.U), ext, normal) 957 } 958 is(ext) { 959 stateReg := Mux(io.validFromIBuf(0) && (uopRes > readyCounter), ext, normal) 960 } 961 } 962 963 val uopRes0 = Mux(stateReg === normal, numOfUop, uopRes) 964 val uopResJudge = Mux(stateReg === normal, 965 io.validFromIBuf(0) && (readyCounter =/= 0.U) && (uopRes0 > readyCounter), 966 io.validFromIBuf(0) && (uopRes0 > readyCounter)) 967 uopRes := Mux(uopResJudge, uopRes0 - readyCounter, 0.U) 968 969 for(i <- 0 until RenameWidth) { 970 decodedInsts(i) := MuxCase(csBundle(i), Seq( 971 (stateReg === normal) -> csBundle(i), 972 (stateReg === ext) -> Mux((i.U + numOfUop -uopRes) < maxUopSize.U, csBundle(i.U + numOfUop - uopRes), csBundle(maxUopSize - 1)) 973 )) 974 } 975 976 977 val validSimple = Wire(Vec(DecodeWidth - 1, Bool())) 978 validSimple.zip(io.validFromIBuf.drop(1).zip(io.isComplex)).map{ case (dst, (src1, src2)) => dst := src1 && !src2 } 979 val notInf = Wire(Vec(DecodeWidth - 1, Bool())) 980 notInf.zip(io.validFromIBuf.drop(1).zip(validSimple)).map{ case (dst, (src1, src2)) => dst := !src1 || src2 } 981 val notInfVec = Wire(Vec(DecodeWidth, Bool())) 982 notInfVec.drop(1).zip(0 until DecodeWidth - 1).map{ case (dst, i) => dst := Cat(notInf.take(i + 1)).andR} 983 notInfVec(0) := true.B 984 985 complexNum := Mux(io.validFromIBuf(0) && readyCounter.orR , 986 Mux(uopRes0 > readyCounter, readyCounter, uopRes0), 987 1.U) 988 validToRename.zipWithIndex.foreach{ 989 case(dst, i) => 990 dst := MuxCase(false.B, Seq( 991 (io.validFromIBuf(0) && uopRes0 > readyCounter ) -> Mux(readyCounter > i.U, true.B, false.B), 992 (io.validFromIBuf(0) && !(uopRes0 > readyCounter)) -> Mux(complexNum > i.U, true.B, validSimple(i.U - complexNum) && notInfVec(i.U - complexNum) && io.readyFromRename(i)), 993 )) 994 } 995 996 readyToIBuf.zipWithIndex.foreach { 997 case (dst, i) => 998 dst := MuxCase(true.B, Seq( 999 (io.validFromIBuf(0) && uopRes0 > readyCounter) -> false.B, 1000 (io.validFromIBuf(0) && !(uopRes0 > readyCounter)) -> (if (i==0) true.B else Mux(RenameWidth.U - complexNum >= i.U, notInfVec(i - 1) && validSimple(i - 1) && io.readyFromRename(i), false.B)), 1001 )) 1002 } 1003 1004 io.deq.decodedInsts := decodedInsts 1005 io.deq.isVset := isVset_u 1006 io.deq.complexNum := complexNum 1007 io.deq.validToRename := validToRename 1008 io.deq.readyToIBuf := readyToIBuf 1009 1010} 1011