fix(amocas): fix amocas.q to avoid stalls (#4435)

when rd is equal to rs1, uop1 will write rd, while uop2 and uop3 of
amocas.q need rs1 as src, which cause a RAW stalls.

However, rs1, the address o

fix(amocas): fix amocas.q to avoid stalls (#4435)

when rd is equal to rs1, uop1 will write rd, while uop2 and uop3 of
amocas.q need rs1 as src, which cause a RAW stalls.

However, rs1, the address of load and store, is used in uop1, we donot
need rs1 in other uops.

show more ...

fix(amocas): re-split uops for amocas to avoid stalls (#4382)

Re-split uops to avoid stalls caused by renaming when rd and rs2 are the
same.

When rd and rs2 are the same, uop1'src will wait uop0'de

fix(amocas): re-split uops for amocas to avoid stalls (#4382)

Re-split uops to avoid stalls caused by renaming when rd and rs2 are the
same.

When rd and rs2 are the same, uop1'src will wait uop0'dest after rename,
which cause stalls.

In this commit, we set src2 in uop0 and dest in uop1, avoiding stalls by
renaming.

show more ...

style(decode): add comments and small modification on code style (#3774)

timing(decode): dequeue uops by indexing in order in DecodeUnitComp (#4025)

feat(Backend): add support for Zacas extension

misc: remove assert temporarily

area(decode): move vecExceptionGen to complex docoder (#3961)

feat(rv64v): support vleff instruction in backend

* use the last uop to update vl
* the vleff instructions are run inorder

rv64v: fix uop split for vfwredsum instructions when lmul==8 (#3430)

rv64v: fix temp vector register index which need to start from 32 (#3358)

Decode: fix assertion's condition of number of uop

* This commit fix the wrong assertion condition which should be `inValid && inUopInfo.numOfUop === 0.U` or `state === s_active && latchedUopInfo.nu

Decode: fix assertion's condition of number of uop

* This commit fix the wrong assertion condition which should be `inValid && inUopInfo.numOfUop === 0.U` or `state === s_active && latchedUopInfo.numOfUop === 0.U`

show more ...

Decode: fix bug of numOfUop is 0 when vector instruction is illegalInst

build: purge chisel 3 and add deprecation check (#3250)

New CSR implementation (#3167)

* CSR is splited into 4 major parts: CSR registers, CSR events, Permission Check and Trap Handler.
* Each CSR is seperated module.
* Add IMSIC module.
* Support new

New CSR implementation (#3167)

* CSR is splited into 4 major parts: CSR registers, CSR events, Permission Check and Trap Handler.
* Each CSR is seperated module.
* Add IMSIC module.
* Support new extensions, such as Sstc, Ssovfpmf and Smaia etc.
* Fix lots of bugs in old implementations, such as wrong permission checks and wrong WARL implementations.

show more ...

Decode: fix readyCounter timing (#3212)

Decode: flush pipe when vstart changed between zero and not zero by CSR inst

Decode: flush pipe when vstart is not zero

rv64v: set flushpipe signal in first uop instead of last uop

rv64v: fix vwsll's imm read and illegal vsew check (#3131)

vsetvl: fix flush and block signal modified by vstart check (#3124)

vstart: support vstart value update and handle vstart exception (#3109)

* after execute vset and vload/vstore(no exception) instructions, set
vstart to zero
* when execute vector instructions exce

vstart: support vstart value update and handle vstart exception (#3109)

* after execute vset and vload/vstore(no exception) instructions, set
vstart to zero
* when execute vector instructions except above instructions, raise
illegal instruction exception
* when modify vstart, blockback and flushpipe

show more ...

rv64v: fix rfWen signal when writing x0 for vector instructions (#3107)

vset: use flushPipe with blockBack for vsetvl instructions

rv64v: fix the wrong dependency caused by uop split

vset: fix old vl read for vsetvl and vsetvli instructions (#3058)

VPU: new vcompress to fit v0&vl split; fix vfredsum/min/max (#3053)

fix vfredsum/max/min:
When the vector vfredusum/max/min consists entirely of inactive elements
and vs1[0] is NaN, the result sho

VPU: new vcompress to fit v0&vl split; fix vfredsum/min/max (#3053)

fix vfredsum/max/min:
When the vector vfredusum/max/min consists entirely of inactive elements
and vs1[0] is NaN, the result should be vs1[0]
When both elements of vfredusum are inactive, the temporary result
changes from positive zero to negative zero.
nes vcompress to fit v0/vl split:
The vcompress calculation combines the ones_sum result with vs1 using a
temporary register to reduce one read operation. Additionally, other
uops, except ones_sum, reduce the basemask calculation and the right
shift basemask operation.
fix vpermtest to fit new vcompress

show more ...