xref: /XiangShan/src/main/scala/xiangshan/backend/decode/isa/bitfield/RiscvInst.scala (revision 5c1681d0ba1d64dd3c2a4b6eae3703364c554743) 
1package xiangshan.backend.decode.isa.bitfield
2
3import chisel3._
4
5abstract class RiscvInst(bitWidth: Int) extends Bundle {
6  val inst: UInt = UInt(bitWidth.W)
7}
8
9class Riscv32BitInst extends RiscvInst(32) {
10  def ALL     : UInt  = inst
11  def OPCODE  : UInt  = inst( 6,  2)
12  def RD      : UInt  = inst(11,  7)
13  def FUNCT3  : UInt  = inst(14, 12)
14  def RS1     : UInt  = inst(19, 15)
15  def RS2     : UInt  = inst(24, 20)
16  def FUNCT7  : UInt  = inst(31, 25)
17}
18
19trait BitFieldsI { this: Riscv32BitInst =>
20  def IMM12   : UInt  = inst(31, 20)
21}
22
23trait BitFieldsS { this: Riscv32BitInst =>
24  def IMM5    : UInt  = inst(11,  7)
25  def IMM7    : UInt  = inst(31, 25)
26}
27
28trait BitFieldsCSR { this: Riscv32BitInst =>
29  def CSRIDX  : UInt  = inst(31, 20)
30  def CSRIMM  : UInt  = inst(19, 15)
31}
32
33trait BitFieldsFp { this: Riscv32BitInst =>
34  def FD      : UInt  = inst(11,  7)
35  def FS1     : UInt  = inst(19, 15)
36  def FS2     : UInt  = inst(24, 20)
37  def FS3     : UInt  = inst(31, 27)
38  def RM      : UInt  = inst(14, 12) // round mode
39  def CONV_SGN: UInt  = inst(24, 20)
40  def FUNCT2  : UInt  = inst(26, 25)
41}
42
43trait BitFieldsVec { this: Riscv32BitInst =>
44  def NF            : UInt  = inst(31, 29)
45  def MEW           : UInt  = inst(28)
46  def MOP           : UInt  = inst(27, 26)
47  def VM            : UInt  = inst(25)
48  def LUMOP         : UInt  = inst(24, 20)
49  def SUMOP         : UInt  = inst(24, 20)
50  def WIDTH         : UInt  = inst(14, 12)
51  def VD            : UInt  = inst(11,  7)
52  def VS1           : UInt  = inst(19, 15)
53  def VS2           : UInt  = inst(24, 20)
54  def VS3           : UInt  = inst(11,  7)
55  def FUNCT6        : UInt  = inst(31 ,26)
56  def ZIMM_VSETVLI  : UInt  = inst(30, 20)
57  def ZIMM_VSETIVLI : UInt  = inst(29, 20)
58  def UIMM_VSETIVLI : UInt  = inst(19, 15)
59  def ZIMM_VTYPE    : UInt  = ZIMM_VSETIVLI(7, 0)
60  def IMM5_OPIVI    : UInt  = inst(19, 15)
61
62  def getInstVType : InstVType = {
63    val res = Wire(new InstVType)
64    res.vlmul := ZIMM_VSETVLI(2, 0)
65    res.vsew  := ZIMM_VSETVLI(5, 3)
66    res.vta   := ZIMM_VSETVLI(6)
67    res.vma   := ZIMM_VSETVLI(7)
68    res
69  }
70}
71
72class XSInstBitFields extends Riscv32BitInst
73  with BitFieldsI
74  with BitFieldsS
75  with BitFieldsCSR
76  with BitFieldsFp
77  with BitFieldsVec
78
79class InstVType extends Bundle {
80  val vma = Bool()
81  val vta = Bool()
82  val vsew = UInt(3.W)
83  val vlmul = UInt(3.W)
84}
85
86