1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17// See LICENSE.SiFive for license details. 18 19package xiangshan.cache 20 21import chipsalliance.rocketchip.config.Parameters 22import chisel3._ 23import chisel3.util._ 24import xiangshan.{HasXSParameter, XSBundle, XSModule} 25 26// this file contains common building blocks that can be shared by ICache and DCache 27// this is the common parameter base for L1 ICache and L1 DCache 28trait L1CacheParameters { 29 def nSets: Int 30 def nWays: Int 31 def rowBits: Int 32 def blockBytes: Int 33} 34 35trait HasL1CacheParameters extends HasXSParameter 36 with MemoryOpConstants { 37 val cacheParams: L1CacheParameters 38 39 def nSets = cacheParams.nSets 40 def nWays = cacheParams.nWays 41 def blockBytes = cacheParams.blockBytes 42 def blockBits = blockBytes * 8 43 44 def idxBits = log2Up(cacheParams.nSets) 45 def wayBits = log2Up(nWays) 46 def blockOffBits = log2Up(cacheParams.blockBytes) 47 48 def untagBits = blockOffBits + idxBits 49 // 4K page 50 def pgIdxBits = 12 51 def pgUntagBits = untagBits min pgIdxBits 52 def tagBits = PAddrBits - pgUntagBits 53 54 // the basic unit at which we store contents 55 // SRAM bank width 56 def rowBits = cacheParams.rowBits 57 def rowBytes = rowBits/8 58 def rowOffBits = log2Up(rowBytes) 59 // the number of rows in a block 60 def blockRows = blockBytes / rowBytes 61 62 // outer bus width 63 def beatBits = l1BusDataWidth 64 def beatBytes = beatBits / 8 65 def refillCycles = blockBytes / beatBytes 66 def beatOffBits = log2Up(beatBytes) 67 68 // inner bus width(determined by XLEN) 69 def wordBits = DataBits 70 def wordBytes = wordBits / 8 71 def wordOffBits = log2Up(wordBytes) 72 // the number of words in a block 73 def blockWords = blockBytes / wordBytes 74 75 def idxMSB = untagBits-1 76 def idxLSB = blockOffBits 77 def offsetmsb = idxLSB-1 78 def offsetlsb = wordOffBits 79 80 def get_tag(addr: UInt) = (addr >> untagBits).asUInt() 81 def get_idx(addr: UInt) = addr(untagBits-1, blockOffBits) 82 def get_block(addr: UInt) = addr >> blockOffBits 83 def get_block_addr(addr: UInt) = (addr >> blockOffBits) << blockOffBits 84 85 def get_beat(addr: UInt) = addr(blockOffBits - 1, beatOffBits) 86 def get_row(addr: UInt) = addr(blockOffBits - 1, rowOffBits) 87 def get_word(addr: UInt) = addr(blockOffBits - 1, wordOffBits) 88 89 def beatRows = beatBits/rowBits 90 def rowWords = rowBits/wordBits 91 92 def full_divide(a: Int, b: Int) = a >= b && isPow2(a / b) 93} 94 95abstract class L1CacheModule(implicit p: Parameters) extends XSModule 96 with HasL1CacheParameters 97 98abstract class L1CacheBundle(implicit p: Parameters) extends XSBundle 99 with HasL1CacheParameters 100