1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import utility._ 24import xiangshan.ExceptionNO._ 25import xiangshan._ 26import xiangshan.backend.Bundles.{MemExuInput, MemExuOutput} 27import xiangshan.backend.fu.PMPRespBundle 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.fu.FuType._ 30import xiangshan.backend.ctrlblock.DebugLsInfoBundle 31import xiangshan.cache.mmu.{TlbCmd, TlbReq, TlbRequestIO, TlbResp} 32import xiangshan.cache.{DcacheStoreRequestIO, DCacheStoreIO, MemoryOpConstants, HasDCacheParameters, StorePrefetchReq} 33 34class StoreUnit(implicit p: Parameters) extends XSModule with HasDCacheParameters { 35 val io = IO(new Bundle() { 36 val redirect = Flipped(ValidIO(new Redirect)) 37 val stin = Flipped(Decoupled(new MemExuInput)) 38 val issue = Valid(new MemExuInput) 39 val tlb = new TlbRequestIO() 40 val dcache = new DCacheStoreIO 41 val pmp = Flipped(new PMPRespBundle()) 42 val lsq = ValidIO(new LsPipelineBundle) 43 val lsq_replenish = Output(new LsPipelineBundle()) 44 val feedback_slow = ValidIO(new RSFeedback) 45 val prefetch_req = Flipped(DecoupledIO(new StorePrefetchReq)) 46 // provide prefetch info to sms 47 val prefetch_train = ValidIO(new StPrefetchTrainBundle()) 48 val stld_nuke_query = Valid(new StoreNukeQueryIO) 49 val stout = DecoupledIO(new MemExuOutput) // writeback store 50 val vecstout = DecoupledIO(new VecPipelineFeedbackIO) 51 // store mask, send to sq in store_s0 52 val st_mask_out = Valid(new StoreMaskBundle) 53 val debug_ls = Output(new DebugLsInfoBundle) 54 // vector 55 val vecstin = Flipped(Decoupled(new VecPipeBundle(isVStore = true))) 56 val vec_isFirstIssue = Input(Bool()) 57 }) 58 59 val s1_ready, s2_ready, s3_ready = WireInit(false.B) 60 61 // Pipeline 62 // -------------------------------------------------------------------------------- 63 // stage 0 64 // -------------------------------------------------------------------------------- 65 // generate addr, use addr to query DCache and DTLB 66 val s0_iss_valid = io.stin.valid 67 val s0_prf_valid = io.prefetch_req.valid && io.dcache.req.ready 68 val s0_vec_valid = io.vecstin.valid 69 val s0_valid = s0_iss_valid || s0_prf_valid || s0_vec_valid 70 val s0_use_flow_vec = s0_vec_valid 71 val s0_use_flow_rs = s0_iss_valid && !s0_vec_valid 72 val s0_use_flow_prf = !s0_iss_valid && !s0_vec_valid && s0_prf_valid 73 val s0_stin = Mux(s0_use_flow_rs, io.stin.bits, 0.U.asTypeOf(io.stin.bits)) 74 val s0_vecstin = Mux(s0_use_flow_vec, io.vecstin.bits, 0.U.asTypeOf(io.vecstin.bits)) 75 val s0_uop = Mux(s0_use_flow_rs, s0_stin.uop, s0_vecstin.uop) 76 val s0_isFirstIssue = s0_use_flow_rs && io.stin.bits.isFirstIssue || s0_use_flow_vec && io.vec_isFirstIssue 77 val s0_rsIdx = Mux(s0_use_flow_rs, io.stin.bits.iqIdx, 0.U) 78 val s0_size = Mux(s0_use_flow_rs || s0_use_flow_vec, s0_uop.fuOpType(2,0), 0.U)// may broken if use it in feature 79 val s0_mem_idx = Mux(s0_use_flow_rs || s0_use_flow_vec, s0_uop.sqIdx.value, 0.U) 80 val s0_rob_idx = Mux(s0_use_flow_rs || s0_use_flow_vec, s0_uop.robIdx, 0.U.asTypeOf(s0_uop.robIdx)) 81 val s0_pc = Mux(s0_use_flow_rs || s0_use_flow_vec, s0_uop.pc, 0.U) 82 val s0_instr_type = Mux(s0_use_flow_rs || s0_use_flow_vec, STORE_SOURCE.U, DCACHE_PREFETCH_SOURCE.U) 83 val s0_wlineflag = Mux(s0_use_flow_rs, s0_uop.fuOpType === LSUOpType.cbo_zero, false.B) 84 val s0_out = Wire(new LsPipelineBundle) 85 val s0_kill = s0_uop.robIdx.needFlush(io.redirect) 86 val s0_can_go = s1_ready 87 val s0_fire = s0_valid && !s0_kill && s0_can_go 88 // vector 89 val s0_vecActive = !s0_use_flow_vec || s0_vecstin.vecActive 90 // val s0_flowPtr = s0_vecstin.flowPtr 91 // val s0_isLastElem = s0_vecstin.isLastElem 92 val s0_secondInv = s0_vecstin.usSecondInv 93 94 // generate addr 95 // val saddr = s0_in.bits.src(0) + SignExt(s0_in.bits.uop.imm(11,0), VAddrBits) 96 val imm12 = WireInit(s0_uop.imm(11,0)) 97 val saddr_lo = s0_stin.src(0)(11,0) + Cat(0.U(1.W), imm12) 98 val saddr_hi = Mux(saddr_lo(12), 99 Mux(imm12(11), s0_stin.src(0)(VAddrBits-1, 12), s0_stin.src(0)(VAddrBits-1, 12)+1.U), 100 Mux(imm12(11), s0_stin.src(0)(VAddrBits-1, 12)+SignExt(1.U, VAddrBits-12), s0_stin.src(0)(VAddrBits-1, 12)), 101 ) 102 val s0_saddr = Cat(saddr_hi, saddr_lo(11,0)) 103 val s0_vaddr = Mux( 104 s0_use_flow_rs, 105 s0_saddr, 106 Mux( 107 s0_use_flow_vec, 108 s0_vecstin.vaddr, 109 io.prefetch_req.bits.vaddr 110 ) 111 ) 112 val s0_mask = Mux( 113 s0_use_flow_rs, 114 genVWmask128(s0_saddr, s0_uop.fuOpType(2,0)), 115 Mux( 116 s0_use_flow_vec, 117 s0_vecstin.mask, 118 // -1.asSInt.asUInt 119 Fill(VLEN/8, 1.U(1.W)) 120 ) 121 ) 122 123 io.tlb.req.valid := s0_valid 124 io.tlb.req.bits.vaddr := s0_vaddr 125 io.tlb.req.bits.cmd := TlbCmd.write 126 io.tlb.req.bits.size := s0_size 127 io.tlb.req.bits.kill := false.B 128 io.tlb.req.bits.memidx.is_ld := false.B 129 io.tlb.req.bits.memidx.is_st := true.B 130 io.tlb.req.bits.memidx.idx := s0_mem_idx 131 io.tlb.req.bits.debug.robIdx := s0_rob_idx 132 io.tlb.req.bits.no_translate := false.B 133 io.tlb.req.bits.debug.pc := s0_pc 134 io.tlb.req.bits.debug.isFirstIssue := s0_isFirstIssue 135 io.tlb.req_kill := false.B 136 137 // Dcache access here: not **real** dcache write 138 // just read meta and tag in dcache, to find out the store will hit or miss 139 140 // NOTE: The store request does not wait for the dcache to be ready. 141 // If the dcache is not ready at this time, the dcache is not queried. 142 // But, store prefetch request will always wait for dcache to be ready to make progress. 143 io.dcache.req.valid := s0_fire 144 io.dcache.req.bits.cmd := MemoryOpConstants.M_PFW 145 io.dcache.req.bits.vaddr := s0_vaddr 146 io.dcache.req.bits.instrtype := s0_instr_type 147 148 s0_out := DontCare 149 s0_out.vaddr := s0_vaddr 150 // Now data use its own io 151 // s1_out.data := genWdata(s1_in.src(1), s1_in.uop.fuOpType(1,0)) 152 s0_out.data := s0_stin.src(1) 153 s0_out.uop := s0_uop 154 s0_out.miss := false.B 155 s0_out.rsIdx := s0_rsIdx 156 s0_out.mask := s0_mask 157 s0_out.isFirstIssue := s0_isFirstIssue 158 s0_out.isHWPrefetch := s0_use_flow_prf 159 s0_out.wlineflag := s0_wlineflag 160 s0_out.isvec := s0_use_flow_vec 161 s0_out.is128bit := false.B 162 s0_out.vecActive := s0_vecActive 163 s0_out.usSecondInv := s0_secondInv 164 when(s0_valid && s0_isFirstIssue) { 165 s0_out.uop.debugInfo.tlbFirstReqTime := GTimer() 166 } 167 168 // exception check 169 val s0_addr_aligned = LookupTree(Mux(s0_use_flow_vec, s0_vecstin.alignedType(1,0), s0_uop.fuOpType(1, 0)), List( 170 "b00".U -> true.B, //b 171 "b01".U -> (s0_out.vaddr(0) === 0.U), //h 172 "b10".U -> (s0_out.vaddr(1,0) === 0.U), //w 173 "b11".U -> (s0_out.vaddr(2,0) === 0.U) //d 174 )) 175 // if vector store sends 128-bit requests, its address must be 128-aligned 176 XSError(s0_use_flow_vec && s0_out.vaddr(3, 0) =/= 0.U && s0_vecstin.alignedType(2), "unit stride 128 bit element is not aligned!") 177 s0_out.uop.exceptionVec(storeAddrMisaligned) := Mux(s0_use_flow_rs || s0_use_flow_vec, !s0_addr_aligned, false.B) 178 179 io.st_mask_out.valid := s0_use_flow_rs 180 io.st_mask_out.bits.mask := s0_out.mask 181 io.st_mask_out.bits.sqIdx := s0_out.uop.sqIdx 182 183 io.stin.ready := s1_ready && s0_use_flow_rs 184 io.vecstin.ready := s1_ready && s0_use_flow_vec 185 io.prefetch_req.ready := s1_ready && io.dcache.req.ready && !s0_iss_valid && !s0_vec_valid 186 187 // Pipeline 188 // -------------------------------------------------------------------------------- 189 // stage 1 190 // -------------------------------------------------------------------------------- 191 // TLB resp (send paddr to dcache) 192 val s1_valid = RegInit(false.B) 193 val s1_in = RegEnable(s0_out, s0_fire) 194 val s1_out = Wire(new LsPipelineBundle) 195 val s1_kill = Wire(Bool()) 196 val s1_can_go = s2_ready 197 val s1_fire = s1_valid && !s1_kill && s1_can_go 198 val s1_vecActive = RegEnable(s0_out.vecActive, true.B, s0_fire) 199 200 // mmio cbo decoder 201 val s1_mmio_cbo = s1_in.uop.fuOpType === LSUOpType.cbo_clean || 202 s1_in.uop.fuOpType === LSUOpType.cbo_flush || 203 s1_in.uop.fuOpType === LSUOpType.cbo_inval 204 val s1_paddr = io.tlb.resp.bits.paddr(0) 205 val s1_tlb_miss = io.tlb.resp.bits.miss 206 val s1_mmio = s1_mmio_cbo 207 val s1_exception = ExceptionNO.selectByFu(s1_out.uop.exceptionVec, StaCfg).asUInt.orR 208 val s1_isvec = RegEnable(s0_out.isvec, false.B, s0_fire) 209 // val s1_isLastElem = RegEnable(s0_isLastElem, false.B, s0_fire) 210 s1_kill := s1_in.uop.robIdx.needFlush(io.redirect) || s1_tlb_miss 211 212 s1_ready := !s1_valid || s1_kill || s2_ready 213 io.tlb.resp.ready := true.B // TODO: why dtlbResp needs a ready? 214 when (s0_fire) { s1_valid := true.B } 215 .elsewhen (s1_fire) { s1_valid := false.B } 216 .elsewhen (s1_kill) { s1_valid := false.B } 217 218 // st-ld violation dectect request. 219 io.stld_nuke_query.valid := s1_valid && !s1_tlb_miss && !s1_in.isHWPrefetch 220 io.stld_nuke_query.bits.robIdx := s1_in.uop.robIdx 221 io.stld_nuke_query.bits.paddr := s1_paddr 222 io.stld_nuke_query.bits.mask := s1_in.mask 223 224 // issue 225 io.issue.valid := s1_valid && !s1_tlb_miss && !s1_in.isHWPrefetch && !s1_isvec 226 io.issue.bits := RegEnable(s0_stin, s0_valid) 227 228 229 // Send TLB feedback to store issue queue 230 // Store feedback is generated in store_s1, sent to RS in store_s2 231 val s1_feedback = Wire(Valid(new RSFeedback)) 232 s1_feedback.valid := s1_valid & !s1_in.isHWPrefetch 233 s1_feedback.bits.hit := !s1_tlb_miss 234 s1_feedback.bits.flushState := io.tlb.resp.bits.ptwBack 235 s1_feedback.bits.robIdx := s1_out.uop.robIdx 236 s1_feedback.bits.sourceType := RSFeedbackType.tlbMiss 237 s1_feedback.bits.dataInvalidSqIdx := DontCare 238 239 XSDebug(s1_feedback.valid, 240 "S1 Store: tlbHit: %d robIdx: %d\n", 241 s1_feedback.bits.hit, 242 s1_feedback.bits.robIdx.value 243 ) 244 245 // io.feedback_slow := s1_feedback 246 247 // get paddr from dtlb, check if rollback is needed 248 // writeback store inst to lsq 249 s1_out := s1_in 250 s1_out.paddr := s1_paddr 251 s1_out.miss := false.B 252 s1_out.mmio := s1_mmio 253 s1_out.tlbMiss := s1_tlb_miss 254 s1_out.atomic := s1_mmio 255 s1_out.uop.exceptionVec(storePageFault) := io.tlb.resp.bits.excp(0).pf.st && s1_vecActive 256 s1_out.uop.exceptionVec(storeAccessFault) := io.tlb.resp.bits.excp(0).af.st && s1_vecActive 257 258 // scalar store and scalar load nuke check, and also other purposes 259 io.lsq.valid := s1_valid && !s1_in.isHWPrefetch 260 io.lsq.bits := s1_out 261 io.lsq.bits.miss := s1_tlb_miss 262 263 // kill dcache write intent request when tlb miss or exception 264 io.dcache.s1_kill := (s1_tlb_miss || s1_exception || s1_mmio || s1_in.uop.robIdx.needFlush(io.redirect)) 265 io.dcache.s1_paddr := s1_paddr 266 267 // write below io.out.bits assign sentence to prevent overwriting values 268 val s1_tlb_memidx = io.tlb.resp.bits.memidx 269 when(s1_tlb_memidx.is_st && io.tlb.resp.valid && !s1_tlb_miss && s1_tlb_memidx.idx === s1_out.uop.sqIdx.value) { 270 // printf("Store idx = %d\n", s1_tlb_memidx.idx) 271 s1_out.uop.debugInfo.tlbRespTime := GTimer() 272 } 273 274 // Pipeline 275 // -------------------------------------------------------------------------------- 276 // stage 2 277 // -------------------------------------------------------------------------------- 278 // mmio check 279 val s2_valid = RegInit(false.B) 280 val s2_in = RegEnable(s1_out, s1_fire) 281 val s2_out = Wire(new LsPipelineBundle) 282 val s2_kill = Wire(Bool()) 283 val s2_can_go = s3_ready 284 val s2_fire = s2_valid && !s2_kill && s2_can_go 285 val s2_vecActive = RegEnable(s1_out.vecActive, true.B, s1_fire) 286 287 s2_ready := !s2_valid || s2_kill || s3_ready 288 when (s1_fire) { s2_valid := true.B } 289 .elsewhen (s2_fire) { s2_valid := false.B } 290 .elsewhen (s2_kill) { s2_valid := false.B } 291 292 val s2_pmp = WireInit(io.pmp) 293 294 val s2_exception = ExceptionNO.selectByFu(s2_out.uop.exceptionVec, StaCfg).asUInt.orR 295 val s2_mmio = s2_in.mmio || s2_pmp.mmio 296 s2_kill := (s2_mmio && !s2_exception) || s2_in.uop.robIdx.needFlush(io.redirect) 297 298 s2_out := s2_in 299 s2_out.mmio := s2_mmio && !s2_exception 300 s2_out.atomic := s2_in.atomic || s2_pmp.atomic 301 s2_out.uop.exceptionVec(storeAccessFault) := (s2_in.uop.exceptionVec(storeAccessFault) || s2_pmp.st) && s2_vecActive 302 303 // kill dcache write intent request when mmio or exception 304 io.dcache.s2_kill := (s2_mmio || s2_exception || s2_in.uop.robIdx.needFlush(io.redirect)) 305 io.dcache.s2_pc := s2_out.uop.pc 306 // TODO: dcache resp 307 io.dcache.resp.ready := true.B 308 309 // feedback tlb miss to RS in store_s2 310 io.feedback_slow.valid := RegNext(s1_feedback.valid && !s1_out.uop.robIdx.needFlush(io.redirect)) && !s2_in.isvec 311 io.feedback_slow.bits := RegNext(s1_feedback.bits) 312 313 val s2_vecFeedback = RegNext(s1_feedback.valid && !s1_out.uop.robIdx.needFlush(io.redirect)) && s2_in.isvec 314 315 // mmio and exception 316 io.lsq_replenish := s2_out 317 318 // prefetch related 319 io.lsq_replenish.miss := io.dcache.resp.fire && io.dcache.resp.bits.miss // miss info 320 321 // RegNext prefetch train for better timing 322 // ** Now, prefetch train is valid at store s3 ** 323 io.prefetch_train.bits.fromLsPipelineBundle(s2_in, latch = true) 324 // override miss bit 325 io.prefetch_train.bits.miss := RegNext(io.dcache.resp.bits.miss) 326 // TODO: add prefetch and access bit 327 io.prefetch_train.bits.meta_prefetch := false.B 328 io.prefetch_train.bits.meta_access := false.B 329 if(EnableStorePrefetchSMS) { 330 io.prefetch_train.valid := RegNext(s2_valid && io.dcache.resp.fire && !s2_out.mmio && !s2_in.tlbMiss && !s2_in.isHWPrefetch) 331 }else { 332 io.prefetch_train.valid := false.B 333 } 334 335 // Pipeline 336 // -------------------------------------------------------------------------------- 337 // stage 3 338 // -------------------------------------------------------------------------------- 339 // store write back 340 val s3_valid = RegInit(false.B) 341 val s3_in = RegEnable(s2_out, s2_fire) 342 val s3_out = Wire(new MemExuOutput(isVector = true)) 343 val s3_kill = s3_in.uop.robIdx.needFlush(io.redirect) 344 val s3_can_go = s3_ready 345 val s3_fire = s3_valid && !s3_kill && s3_can_go 346 val s3_vecFeedback = RegEnable(s2_vecFeedback, s2_fire) 347 348 when (s2_fire) { s3_valid := (!s2_mmio || s2_exception) && !s2_out.isHWPrefetch } 349 .elsewhen (s3_fire) { s3_valid := false.B } 350 .elsewhen (s3_kill) { s3_valid := false.B } 351 352 // wb: writeback 353 val SelectGroupSize = RollbackGroupSize 354 val lgSelectGroupSize = log2Ceil(SelectGroupSize) 355 val TotalSelectCycles = scala.math.ceil(log2Ceil(LoadQueueRAWSize).toFloat / lgSelectGroupSize).toInt + 1 356 357 s3_out := DontCare 358 s3_out.uop := s3_in.uop 359 s3_out.data := DontCare 360 s3_out.debug.isMMIO := s3_in.mmio 361 s3_out.debug.paddr := s3_in.paddr 362 s3_out.debug.vaddr := s3_in.vaddr 363 s3_out.debug.isPerfCnt := false.B 364 365 // Pipeline 366 // -------------------------------------------------------------------------------- 367 // stage x 368 // -------------------------------------------------------------------------------- 369 // delay TotalSelectCycles - 2 cycle(s) 370 val TotalDelayCycles = TotalSelectCycles - 2 371 val sx_valid = Wire(Vec(TotalDelayCycles + 1, Bool())) 372 val sx_ready = Wire(Vec(TotalDelayCycles + 1, Bool())) 373 val sx_in = Wire(Vec(TotalDelayCycles + 1, new VecMemExuOutput(isVector = true))) 374 375 // backward ready signal 376 s3_ready := sx_ready.head 377 for (i <- 0 until TotalDelayCycles + 1) { 378 if (i == 0) { 379 sx_valid(i) := s3_valid 380 sx_in(i).output := s3_out 381 sx_in(i).vecFeedback := s3_vecFeedback 382 sx_in(i).mmio := s3_in.mmio 383 sx_in(i).usSecondInv := s3_in.usSecondInv 384 // sx_in(i).elemIdx := s3_in.elemIdx 385 // sx_in(i).alignedType := s3_in.alignedType 386 sx_ready(i) := !s3_valid(i) || sx_in(i).output.uop.robIdx.needFlush(io.redirect) || (if (TotalDelayCycles == 0) io.stout.ready else sx_ready(i+1)) 387 } else { 388 val cur_kill = sx_in(i).output.uop.robIdx.needFlush(io.redirect) 389 val cur_can_go = (if (i == TotalDelayCycles) io.stout.ready else sx_ready(i+1)) 390 val cur_fire = sx_valid(i) && !cur_kill && cur_can_go 391 val prev_fire = sx_valid(i-1) && !sx_in(i-1).output.uop.robIdx.needFlush(io.redirect) && sx_ready(i) 392 393 sx_ready(i) := !sx_valid(i) || cur_kill || (if (i == TotalDelayCycles) io.stout.ready else sx_ready(i+1)) 394 val sx_valid_can_go = prev_fire || cur_fire || cur_kill 395 sx_valid(i) := RegEnable(Mux(prev_fire, true.B, false.B), false.B, sx_valid_can_go) 396 sx_in(i) := RegEnable(sx_in(i-1), prev_fire) 397 } 398 } 399 val sx_last_valid = sx_valid.takeRight(1).head 400 val sx_last_ready = sx_ready.takeRight(1).head 401 val sx_last_in = sx_in.takeRight(1).head 402 sx_last_ready := !sx_last_valid || sx_last_in.output.uop.robIdx.needFlush(io.redirect) || io.stout.ready 403 404 io.stout.valid := sx_last_valid && !sx_last_in.output.uop.robIdx.needFlush(io.redirect) && isStore(sx_last_in.output.uop.fuType) 405 io.stout.bits := sx_last_in.output 406 407 io.vecstout.valid := sx_last_valid && !sx_last_in.output.uop.robIdx.needFlush(io.redirect) && isVStore(sx_last_in.output.uop.fuType) 408 // TODO: implement it! 409 io.vecstout.bits.mBIndex := DontCare 410 io.vecstout.bits.hit := !sx_last_in.vecFeedback 411 io.vecstout.bits.isvec := true.B 412 io.vecstout.bits.sourceType := RSFeedbackType.tlbMiss 413 io.vecstout.bits.mmio := sx_last_in.mmio 414 io.vecstout.bits.exceptionVec := sx_last_in.output.uop.exceptionVec 415 io.vecstout.bits.usSecondInv := sx_last_in.usSecondInv 416 // io.vecstout.bits.reg_offset.map(_ := DontCare) 417 // io.vecstout.bits.elemIdx.map(_ := sx_last_in.elemIdx) 418 // io.vecstout.bits.elemIdxInsideVd.map(_ := DontCare) 419 // io.vecstout.bits.vecdata.map(_ := DontCare) 420 // io.vecstout.bits.mask.map(_ := DontCare) 421 // io.vecstout.bits.alignedType.map(_ := sx_last_in.alignedType) 422 423 io.debug_ls := DontCare 424 io.debug_ls.s1.isTlbFirstMiss := io.tlb.resp.valid && io.tlb.resp.bits.miss && io.tlb.resp.bits.debug.isFirstIssue && !s1_in.isHWPrefetch 425 io.debug_ls.s1_robIdx := s1_in.uop.robIdx.value 426 427 private def printPipeLine(pipeline: LsPipelineBundle, cond: Bool, name: String): Unit = { 428 XSDebug(cond, 429 p"$name" + p" pc ${Hexadecimal(pipeline.uop.pc)} " + 430 p"addr ${Hexadecimal(pipeline.vaddr)} -> ${Hexadecimal(pipeline.paddr)} " + 431 p"op ${Binary(pipeline.uop.fuOpType)} " + 432 p"data ${Hexadecimal(pipeline.data)} " + 433 p"mask ${Hexadecimal(pipeline.mask)}\n" 434 ) 435 } 436 437 printPipeLine(s0_out, s0_valid, "S0") 438 printPipeLine(s1_out, s1_valid, "S1") 439 440 // perf cnt 441 XSPerfAccumulate("s0_in_valid", s0_valid) 442 XSPerfAccumulate("s0_in_fire", s0_fire) 443 XSPerfAccumulate("s0_in_fire_first_issue", s0_fire && s0_isFirstIssue) 444 XSPerfAccumulate("s0_addr_spec_success", s0_fire && !s0_use_flow_vec && s0_saddr(VAddrBits-1, 12) === s0_stin.src(0)(VAddrBits-1, 12)) 445 XSPerfAccumulate("s0_addr_spec_failed", s0_fire && !s0_use_flow_vec && s0_saddr(VAddrBits-1, 12) =/= s0_stin.src(0)(VAddrBits-1, 12)) 446 XSPerfAccumulate("s0_addr_spec_success_once", s0_fire && !s0_use_flow_vec && s0_saddr(VAddrBits-1, 12) === s0_stin.src(0)(VAddrBits-1, 12) && s0_isFirstIssue) 447 XSPerfAccumulate("s0_addr_spec_failed_once", s0_fire && !s0_use_flow_vec && s0_saddr(VAddrBits-1, 12) =/= s0_stin.src(0)(VAddrBits-1, 12) && s0_isFirstIssue) 448 449 XSPerfAccumulate("s1_in_valid", s1_valid) 450 XSPerfAccumulate("s1_in_fire", s1_fire) 451 XSPerfAccumulate("s1_in_fire_first_issue", s1_fire && s1_in.isFirstIssue) 452 XSPerfAccumulate("s1_tlb_miss", s1_fire && s1_tlb_miss) 453 XSPerfAccumulate("s1_tlb_miss_first_issue", s1_fire && s1_tlb_miss && s1_in.isFirstIssue) 454 // end 455}